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Национальный исследовательский университет «МИЭТ»

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Архитектура и программирование микроконтроллеров

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Архитектура и программирование микроконтроллеров (Шипатов) 2024 (Отсутствуют некоторые файлы, но все лабы вроде на месте) / Labs / Docs / STM / PM0253 STM32 F7 H7 Cortex-M7 prog man.pdf

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The Cortex-M7 processor				PM0253

	Table 1. Summary of processor mode, execution privilege level, and stack use
			options
	Processor mode	Used to execute	Privilege level for	Stack used
	Processor mode	Used to execute	software execution	Stack used
			software execution

	Thread	Applications	Privileged or unprivileged(1)	Main stack or process stack(1)
	Handler	Exception handlers	Always privileged	Main stack

1. See CONTROL register on page 27.

2.1.3Core registers

The processor core registers are

Figure 2. Processor core registers

Low registers

General-purpose

registers

High registers

R10

R11

R12

Stack Pointer

PSP‡

MSP‡

‡Banked version of SP

SP (R13)

Link Register

LR (R14)

Program Counter

PC (R15)

PSR

Program status register

PRIMASK

FAULTMASK

Exception mask registers

Special registers

BASEPRI

CONTROL register

CONTROL

MSv39636V1

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PM0253 Rev 5

PM0253						The Cortex-M7 processor

	Table 2. Core register set summary
Register	Name	Type	(1)	Required	Reset value	Description
Register	Name	Type		privilege(2)	Reset value	Description
General-purpose registers	R0-R12	RW		Either	Unknown	General-purpose registers on
General-purpose registers	R0-R12	RW		Either	Unknown	page 21.
						page 21.

Stack pointer	MSP	RW		Either	See	Stack pointer on page 21.
Stack pointer	MSP	RW		Either	description	Stack pointer on page 21.
					description

Stack pointer	PSP	RW		Either	Unknown	Stack pointer on page 21

Link register	LR	RW		Either	0xFFFFFFFF	Link register on page 21

Program counter	PC	RW		Either	See	Program counter on page 22
Program counter	PC	RW		Either	description	Program counter on page 22
					description

Program status register	PSR	RW		Either	0x01000000(3)	Program status register on
Program status register	PSR	RW		Either	0x01000000(3)	page 22
						page 22

Application program status	APSR	RW		Either	Unknown	Application program status
register						register on page 23
Interrupt program status	IPSR	RO		Privileged	0x00000000	Interrupt program status register
register	IPSR	RO		Privileged	0x00000000	on page 23
register						on page 23

Execution program Status	EPSR	RO		Privileged	0x01000000(3)	Execution program status
register	EPSR	RO		Privileged	0x01000000(3)	register on page 24
register						register on page 24

Priority mask register	PRIMASK	RW		Privileged	0x00000000	Priority mask register on
Priority mask register	PRIMASK	RW		Privileged	0x00000000	page 25
						page 25

Fault mask register	FAULTMASK	RW		Privileged	0x00000000	Fault mask register on page 26

Base priority mask register	BASEPRIS	RW		Privileged	0x00000000	Priority mask register on
Base priority mask register	BASEPRIS	RW		Privileged	0x00000000	page 25
						page 25

Control register	CONTROL	RW		Privileged	0x00000000	CONTROL register on page 27

1.Describes access type during program execution in Thread mode and Handler mode. Debug access can differ.

2.An entry of Either means privileged and unprivileged software can access the register.

3.The EPSR reads as zero when executing an MRS instruction.

General-purpose registers

R0-R12 are 32-bit general-purpose registers for data operations.

Stack pointer

The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use:

•0 = Main Stack Pointer (MSP). This is the reset value.

•1 = Process Stack Pointer (PSP).

On reset, the processor loads the MSP with the value from address 0x00000000.

Link register

The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor sets the LR value to 0xFFFFFFFF.

PM0253 Rev 5

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The Cortex-M7 processor	PM0253

Program counter

The Program Counter (PC) is register R15. It contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.

Program status register

The Program Status register (PSR) combines:

•Application Program Status register (APSR).

•Interrupt Program Status register (IPSR).

•Execution Program Status register (EPSR).

These registers are mutually exclusive bit fields in the 32-bit PSR. The bit assignments are

Figure 3. APSR, IPSR and EPSR bit assignments

31 30 29 28 27 26 25 24 23

20 19

16 15

APSR

Reserved

GE[3:0]

Reserved

IPSR

Reserved

ISR_NUMBER

EPSR

Reserved

ICI/IT

Reserved

ICI/IT

Reserved

MSv39637V1

Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example:

•Read all of the registers using PSR with the MRS instruction.

•Write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with the MSR instruction.

The PSR combinations and attributes are:

Table 3. PSR register combinations

	Register		Type	Combination

PSR		RW(1),(2)		APSR, EPSR, and IPSR.

IEPSR		RO		EPSR and IPSR.

IAPSR		RW(1)		APSR and IPSR.
EAPSR		RW(2)		APSR and EPSR.

1.The processor ignores writes to the IPSR bits.

2.Reads of the EPSR bits return zero, and the processor ignores writes to these bits.

See the instruction descriptions MRS on page 178 and MSR on page 179 for more information about how to access the program status registers.

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PM0253 Rev 5

PM0253	The Cortex-M7 processor

Application program status register

The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 4 on page 23 for its attributes. The bit assignments are:

		Table 4. APSR bit assignments
Bits	Name	Description

[31]	N	Negative flag.

[30]	Z	Zero flag.

[29]	C	Carry or borrow flag.

[28]	V	Overflow flag.

[27]	Q	DSP overflow and saturation flag

[26:20]	-	Reserved

[19:16]	GE[3:0]	Greater than or Equal flags. See SEL on page 108 for more
[19:16]	GE[3:0]	information.
		information.

[15:0]	-	Reserved

Interrupt program status register

The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 5 on page 24 for its attributes. The bit assignments are:

PM0253 Rev 5

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2.1.3Core registers

Figure 2. Processor core registers

Table 2. Core register set summary

Figure 3. APSR, IPSR and EPSR bit assignments

Table 3. PSR register combinations

Table 4. APSR bit assignments