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Национальный исследовательский университет «МИЭТ»

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Архитектура и программирование микроконтроллеров

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Архитектура и программирование микроконтроллеров (Шипатов) 2024 (Отсутствуют некоторые файлы, но все лабы вроде на месте) / Labs / Docs / STM / PM0214 STM32 Cortex-M4 prog man.pdf

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Core peripherals	PM0214

4.3Nested vectored interrupt controller (NVIC)

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports:

•Up to 240 interrupts

•A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority

•Level and pulse detection of interrupt signals

•Dynamic reprioritization of interrupts

•Grouping of priority values into group priority and subpriority fields

•Interrupt tail-chaining

•An external Non-maskable interrupt (NMI)

The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. The hardware implementation of the NVIC registers is:

Table 45. NVIC register summary

Address		Name	Type	Required	Reset value	Description
Address		Name	Type	privilege	Reset value	Description
				privilege

0xE000E100-		NVIC_ISER0-	RW	Privileged	0x00000000	Table 4.3.2: Interrupt set-enable register x
0xE000E11F		NVIC_ISER7	RW	Privileged	0x00000000	(NVIC_ISERx) on page 210

0XE000E180-		NVIC_ICER0-	RW	Privileged	0x00000000	Table 4.3.3: Interrupt clear-enable register x
0xE000E19F		NVIC_ICER7	RW	Privileged	0x00000000	(NVIC_ICERx) on page 211

0XE000E200-		NVIC_ISPR0-	RW	Privileged	0x00000000	Table 4.3.4: Interrupt set-pending register x
0xE000E21F		NVIC_ISPR7				(NVIC_ISPRx) on page 212
0XE000E280-		NVIC_ICPR0-	RW	Privileged	0x00000000	Table 4.3.5: Interrupt clear-pending register x
0xE000E29F		NVIC_ICPR7	RW	Privileged	0x00000000	(NVIC_ICPRx) on page 213

0xE000E300-		NVIC_IABR0-	RW	Privileged	0x00000000	Table 4.3.6: Interrupt active bit register x
0xE000E31F		NVIC_IABR7	RW	Privileged	0x00000000	(NVIC_IABRx) on page 214

0xE000E400-		NVIC_IPR0-	RW	Privileged	0x00000000	Table 4.3.7: Interrupt priority register x
0xE000E4EF		NVIC_IPR59				(NVIC_IPRx) on page 215
0xE000EF00		STIR	WO	Configurable	0x00000000	Table 4.3.8: Software trigger interrupt register
						(NVIC_STIR) on page 216
Note:	The number of interrupts is product-dependent. Refer to reference manual/datasheet of
	relevant STM32 product for related information.

208/262

PM0214 Rev 10

PM0214	Core peripherals

4.3.1Accessing the Cortex-M4 NVIC registers using CMSIS

CMSIS functions enable software portability between different Cortex-M profile processors. To access the NVIC registers when using CMSIS, use the following functions:

Table 46. CMSIS access NVIC functions

	CMSIS function(1)	Description
	void NVIC_EnableIRQ(IRQn_Type IRQn)	Enables an interrupt or exception.

	void NVIC_DisableIRQ(IRQn_Type IRQn)	Disables an interrupt or exception.

	void NVIC_SetPendingIRQ(IRQn_Type IRQn)	Sets the pending status of interrupt or
	void NVIC_SetPendingIRQ(IRQn_Type IRQn)	exception to 1.
		exception to 1.

	void NVIC_ClearPendingIRQ(IRQn_Type IRQn)	Clears the pending status of interrupt or
	void NVIC_ClearPendingIRQ(IRQn_Type IRQn)	exception to 0.
		exception to 0.

		Reads the pending status of interrupt or
	uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)	exception. This function returns non-
	uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)	zero value if the pending status is set to
		zero value if the pending status is set to
		1.

		Sets the priority of an interrupt or
	void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)	exception with configurable priority level
		to 1.

		Reads the priority of an interrupt or
	uint32_t NVIC_GetPriority(IRQn_Type IRQn)	exception with configurable priority
	uint32_t NVIC_GetPriority(IRQn_Type IRQn)	level. This function return the current
		level. This function return the current
		priority level.

1.The input parameter IRQn is the IRQ number. Possible “n” values depend on product. Refer to reference manual/datasheet of relevant STM32 product for related information.

PM0214 Rev 10

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Core peripherals	PM0214

4.3.2Interrupt set-enable register x (NVIC_ISERx)

Address offset: 0x100 + 0x04 * x, (x = 0 to 7) Reset value: 0x0000 0000

Required privilege: Privileged

NVIC_ISER0 bits 0 to 31 are for interrupt 0 to 31, respectively NVIC_ISER1 bits 0 to 31 are for interrupt 32 to 63, respectively

....

NVIC_ISER6 bits 0 to 31 are for interrupt 192 to 223, respectively NVIC_ISER7 bits 0 to 15 are for interrupt 224 to 239, respectively

SETENA[31:16]

SETENA[15:0]

Bits 31:0

SETENA: Interrupt set-enable bits.

Write:

0: No effect

1: Enable interrupt

Read:

0: Interrupt disabled

1: Interrupt enabled.

If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an

interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending,

but the NVIC never activates the interrupt, regardless of its priority.

Bits 16 to 31 of the NVIC_ISER7 register are reserved.

Note:

The number of interrupts is product-dependent. Refer to reference manual/datasheet of

relevant STM32 product for related information.

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PM0214 Rev 10

PM0214	Core peripherals

4.3.3Interrupt clear-enable register x (NVIC_ICERx)

Address offset: 0x180 + 0x04 * x, (x = 0 to 7) Reset value: 0x0000 0000

Required privilege: Privileged

NVIC_ICER0 bits 0 to 31 are for interrupt 0 to 31, respectively NVIC_ICER1 bits 0 to 31 are for interrupt 32 to 63, respectively

....

NVIC_ICER6 bits 0 to 31 are for interrupt 192 to 223, respectively NVIC_ICER7 bits 0 to 15 are for interrupt 224 to 239, respectively

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

							CLRENA[31:16]

rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

							CLRENA[15:0]

rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:0 CLRENA: Interrupt clear-enable bits.

Write:

0:No effect

1:Disable interrupt

Read:

0:Interrupt disabled

1:Interrupt enabled.

Bits 16 to 31 of the NVIC_ICER7 register are reserved.

Note:	The number of interrupts is product-dependent. Refer to reference manual/datasheet of
	relevant STM32 product for related information.

PM0214 Rev 10

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Core peripherals	PM0214

4.3.4Interrupt set-pending register x (NVIC_ISPRx)

Address offset: 0x200 + 0x04 * x, (x = 0 to 7) Reset value: 0x0000 0000

Required privilege: Privileged

NVIC_ISPR0 bits 0 to 31 are for interrupt 0 to 31, respectively NVIC_ISPR1 bits 0 to 31 are for interrupt 32 to 63, respectively

....

NVIC_ISPR6 bits 0 to 31 are for interrupt 192 to 223, respectively NVIC_ISPR7 bits 0 to 15 are for interrupt 224 to 239, respectively

SETPEND[31:16]

SETPEND[15:0]

Bits 31:0

SETPEND: Interrupt set-pending bits

Write:

0: No effect

1: Changes interrupt state to pending

Read:

0: Interrupt is not pending

1: Interrupt is pending

Writing 1 to the ISPR bit corresponding to an interrupt that is pending has no effect.

Writing 1 to the ISPR bit corresponding to a disabled interrupt sets the state of that interrupt to

pending.

Bits 16 to 31 of the NVIC_ISPR7 register are reserved.

Note:

The number of interrupts is product-dependent. Refer to reference manual/datasheet of

relevant STM32 product for related information.

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PM0214 Rev 10

PM0214	Core peripherals

4.3.5Interrupt clear-pending register x (NVIC_ICPRx)

Address offset: 0x280 + 0x04 * x, (x = 0 to 7) Reset value: 0x0000 0000

Required privilege: Privileged

NVIC_ICPR0 bits 0 to 31 are for interrupt 0 to 31, respectively NVIC_ICPR1 bits 0 to 31 are for interrupt 32 to 63, respectively

....

NVIC_ICPR6 bits 0 to 31 are for interrupt 192 to 223, respectively NVIC_ICPR7 bits 0 to 15 are for interrupt 224 to 239, respectively

31	30	29	28	27		26	25	24	23		22	21	20	19	18	17	16

								CLRPEND[31:16]

rc_w1	rc_w1	rc_w1	rc_w1	rc_w1		rc_w1	rc_w1	rc_w1	rc_w1		rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

15	14	13	12	11		10	9	8	7		6	5	4	3	2	1	0

								CLRPEND[15:0]

rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1		rc_w1	rc_w1	rc_w1	rc_w1		rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

	Bits 31:0		CLRPEND: Interrupt clear-pending bits
			Write:
			0: No effect
			1: Removes the pending state of an interrupt
			Read:
			0: Interrupt is not pending
			1: Interrupt is pending
			Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
			Bits 16 to 31 of the NVIC_ICPR7 register are reserved.
Note:		The number of interrupts is product-dependent. Refer to reference manual/datasheet of
		relevant STM32 product for related information.

PM0214 Rev 10

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