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;of R2, saturates to 16 bits, writes to corresponding
;halfword of R4
QSUB8 R4, R2, R5 ; |
Subtracts |
bytes of R5 from the |
corresponding |
byte |
in R2 |
; |
saturates |
to 8 bits, writes to |
corresponding |
byte |
ofR4. |
3.7.4QASX and QSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed.
Syntax
op{cond} {Rd}, Rm, Rn
Where:
•op’ is one of:
QASX Add and Subtract with Exchange and Saturate. QSAX Subtract and Add with Exchange and Saturate.
•‘cond’ is an optional condition code (see Conditional execution on page 65)
•‘Rd’ is the destination register.
•‘Rn, Rm’ are registers holding the first and second operands.
Operation
The QASX instruction:
1.Adds the top halfword of the source operand with bottom halfword of second operand.
2.Subtracts the top halfword of second operand from bottom highword of first operand.
3.Saturates the result of the subtraction and writes a 16-bit signed integer in the range – 215 ≤ x ≤ 215 – 1, where x equals 16, to the bottom halfword of the destination register.
4.Saturates the results of the sum and writes a 16-bit signed integer in the range
5.–215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register.
The QSAX instruction:
1.Subtracts the bottom halfword of second operand from top highword of first operand.
2.Adds the bottom halfword of source operand with top halfword of second operand.
3.Saturates the results of the sum and writes a 16-bit signed integer in the range
4.–215 ≤ x ≤ 215 – 1, where x equals 16, to the bottom halfword of the destination register.
5.Saturates the result of the subtraction and writes a 16-bit signed integer in the range – 215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition flags
These instructions do not affect the condition code flags.
Examples
QASX |
R7, R4, R2 |
; Adds top halfword of R4 to bottom halfword of R2, |
; saturates to 16 bits, writes to top halfword of R7
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;Subtracts top highword of R2 from bottom halfword of
;R4, saturates to 16 bits and writes to bottom halfword
;of R7
QSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of
;R3, saturates to 16 bits, writes to top halfword of R0
;Adds bottom halfword of R3 to top halfword of R5,
;saturates to 16 bits, writes to bottom halfword of R0.
3.7.5QDADD and QDSUB
Saturating Double and Add and Saturating Double and Subtract, signed.
Syntax
op{cond} {Rd}, Rm, Rn
Where:
•op’ is one of:
QDADD Saturating Double and Add. QDSUB Saturating Double and Subtract.
•‘cond’ is an optional condition code (see Conditional execution on page 65)
•‘Rd’ is the destination register.
•‘Rn, Rm’ are registers holding the first and second operands.
Operation
The QDADD instruction:
1.Doubles the second operand value.
2.Adds the result of the doubling to the signed saturated value in the first operand.
3.Writes the result to the destination register.
The QDSUB instruction:
1.Doubles the second operand value.
2.Subtracts the doubled value from the signed saturated value in the first operand.
3.Writes the result to the destination register.
Both the doubling and the addition or subtraction have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231– 1. If saturation occurs in either operation, it sets the Q flag in the APSR.
Restrictions
Do not use SP and do not use PC.
Condition flags
If saturation occurs, these instructions set the Q flag to 1.
Examples
QDADD |
R7, |
R4, |
R2 |
; Doubles and saturates |
R4 to 32 bits, adds R2, |
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; saturates |
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writes to R7 |
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QDSUB |
R0, |
R3, |
R5 |
; Subtracts |
R3 |
doubled and saturated |
to 32 bits |
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3.7.6 |
UQASX and UQSAX |
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned.
Syntax
op{cond} {Rd}, Rm, Rn
Where:
• op’ is one of:
UQASX Add and Subtract with Exchange and Saturate. UQSAX Subtract and Add with Exchange and Saturate.
• ‘cond’ is an optional condition code (see Conditional execution on page 65)
• ‘Rd’ is the destination register.
• ‘Rn, Rm’ are registers holding the first and second operands.
Operation
The UQASX instruction:
1.Adds the bottom halfword of the source operand with top halfword of second operand.
2.Subtracts the bottom halfword of the second operand from the top highword of the first operand.
3.Saturates the results of the sum and writes a 16-bit unsigned integer in the range
4.0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register.
5.Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the bottom halfword of the destination register.
The UQSAX instruction:
1.Subtracts the bottom halfword of second operand from top highword of first operand.
2.Adds the bottom halfword of the first operand with the top halfword of the second operand.
3.Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register.
4.Saturates the results of the addition and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition flags
These instructions do not affect the condition code flags.
Examples
UQASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2,
;saturates to 16 bits, writes to top halfword of R7
;Subtracts top halfword of R2 from bottom halfword of
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; R4, saturates to 16 bits, writes to bottom halfword of R7 UQSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of
;R3, saturates to 16 bits, writes to top halfword of R0
;Adds bottom halfword of R4 to top halfword of R5
;saturates to 16 bits, writes to bottom halfword of R0.
3.7.7UQADD and UQSUB
Saturating Add and Saturating Subtract Unsigned.
Syntax
op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
Where:
•op’ is one of:
UQADD8 Saturating four unsigned 8-bit integer additions. UQADD16 Saturating two unsigned 16-bit integer additions. UDSUB8 Saturating four unsigned 8-bit integer subtractions. UQSUB16 Saturating two unsigned 16-bit integer subtractions.
•‘cond’ is an optional condition code (see Conditional execution on page 65)
•‘Rd’ is the destination register.
•‘Rn, Rm’ are registers holding the first and second operands.
Operation
These instructions add or subtract two or four values and then writes an unsigned saturated value in the destination register.
The UQADD16 instruction:
1.Adds the respective top and bottom halfwords of the first and second operands.
2.Saturates the result of the additions for each halfword in the destination register to the unsigned range 0 ≤ x ≤ 216-1, where x is 16.
The UQADD8 instruction:
1.Adds each respective byte of the first and second operands.
2.Saturates the result of the addition for each byte in the destination register to the unsigned range 0 ≤ x ≤ 28-1, where x is 8.
The UQSUB16 instruction:
1.Subtracts both halfwords of the second operand from the respective halfwords of the first operand.
2.Saturates the result of the differences in the destination register to the unsigned range 0 ≤ x ≤ 216-1, where x is 16.
The UQSUB8 instructions:
1.Subtracts the respective bytes of the second operand from the respective bytes of the first operand.
2.Saturates the results of the differences for each byte in the destination register to the unsigned range 0 ≤ x ≤ 28-1, where x is 8.
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Restrictions
Do not use SP and do not use PC.
Condition flags
These instructions do not affect the condition code flags.
Examples
UQADD16 R7, R4, R2; Adds halfwords in R4 to corresponding halfword in R2,
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saturates to 16 bits, writes to corresponding halfword |
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of R7 |
UQADD8 |
R4, R2, R5 |
; Adds bytes of R2 to corresponding byte of R5, saturates |
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to 8 bits, writes to corresponding bytes of R4 |
UQSUB16 R6, R3, R0 |
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Subtracts halfwords in R0 from corresponding halfword |
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in R3, saturates to 16 bits, writes to corresponding |
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halfword in R6 |
UQSUB8 |
R1, R5, R6 |
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Subtracts bytes in R6 from corresponding byte of R5, |
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