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The STM32 Cortex-M4 instruction set |
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3.5.7MOVT
Move Top.
Syntax
MOVT{cond} Rd, #imm16
Where:
•‘cond’ is an optional condition code (see Conditional execution on page 65).
•‘Rd’ is the destination register.
•‘imm16’ is a 16-bit immediate constant.
Operation
MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0].
The MOV, MOVT instruction pair enables you to generate any 32-bit constant.
Restrictions
Rd must be neither SP nor PC.
Condition flags
This instruction does not change the flags.
Examples
MOVT R3, #0xF123 ; write 0xF123 to upper halfword of R3,
; lower halfword and APSR are unchanged
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3.5.8REV, REV16, REVSH, and RBIT
Reverse bytes and Reverse bits.
Syntax
op{cond} Rd, Rn
Where:
•‘op’ is one of the following:
REV: Reverse byte order in a word.
REV16: Reverse byte order in each halfword independently.
REVSH: Reverse byte order in the bottom halfword, and sign extends to 32 bits. RBIT: Reverse the bit order in a 32-bit word.
•‘cond’ is an optional condition code, see Conditional execution on page 65.
•‘Rd’ is the destination register.
•‘Rn’ is the register holding the operand.
Operation
Use these instructions to change endianness of data:
•REV: Converts either:
–32-bit big-endian data into little-endian data
–or 32-bit little-endian data into big-endian data.
•REV16: Converts either:
–16-bit big-endian data into little-endian data
–or 16-bit little-endian data into big-endian data.
•REVSH: Converts either:
–16-bit signed big-endian data into 32-bit signed little-endian data
–or 16-bit signed little-endian data into 32-bit signed big-endian data.
Restrictions
Do not use either SP or PC.
Condition flags
These instructions do not change the flags.
Examples
REV R3, R7 ; reverse byte order of value in R7 and write it to R3 REV16 R0, R0 ; reverse byte order of each 16-bit halfword in R0 REVSH R0, R5 ; reverse Signed Halfword
REVHS R3, R7 ; reverse with Higher or Same condition
RBIT R7, R8 ; reverse bit order of value in R8 and write result to R7
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3.5.9SADD16 and SADD8
Signed Add 16 and Signed Add 8
Syntax
op{cond}{Rd,} Rn, Rm
Where:
•op is any of the following:
SADD16: Performs two 16-bit signed integer additions. SADD8: Performs four 8-bit signed integer additions.
•‘cond’ is an optional condition code (see Conditional execution on page 65).
•‘Rd’ is the destination register.
•‘Rn’ is the register holding the operand.
•‘Rm’ is the second register holding the operand.
Operation
Use these instructions to perform a halfword or byte add in parallel:
The SADD16 instruction:
1.Adds each halfword from the first operand to the corresponding halfword of the second operand.
2.Writes the result in the corresponding halfwords of the destination register.
The SADD8 instruction:
1.Adds each byte of the first operand to the corresponding byte of the second operand.
2.Writes the result in the corresponding bytes of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition flags
These instructions do not change the flags.
Examples
SADD16 R1, R0 ; Adds the halfwords in R0 to the corresponding halfword ; of R1 and writes to corresponding halfword of R1.
SADD8 R4, R0, R5 ; Adds bytes of R0 to the corresponding byte in R5 and ; writes to the corresponding byte in R4.
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3.5.10SHADD16 and SHADD8
Signed Halving Add 16 and Signed Halving Add 8
Syntax
op{cond}{Rd,} Rn, Rm
Where:
•op is any of the following: SHADD16: Signed halving add 16. SHADD8: Signed halving add 8.
•‘cond’ is an optional condition code (see Conditional execution on page 65).
•‘Rd’ is the destination register.
•‘Rn’ is the register holding the operand.
•‘Rm’ is the second operand register.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination register:
The SHADD16 instruction:
1.Adds each halfword from the first operand to the corresponding halfword of the second operand.
2.Shuffles the result by one bit to the right, halving the data.
3.Writes the halfword results in the destination register.
The SHADDB8 instruction:
1.Adds each byte of the first operand to the corresponding byte of the second operand.
2.Shuffles the result by one bit to the right, halving the data.
3.Writes the byte results in the destination register.
Restrictions
Do not use SP and do not use PC.
Condition flags
These instructions do not change the flags.
Examples
SHADD16 R1, R0 ; Adds halfwords in R0 to corresponding halfword of R1 & ; writes halved result to corresponding halfword in R1
SHADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and ; writes halved result to corresponding byte in R4.
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