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Национальный исследовательский университет «МИЭТ»

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Архитектура и программирование микроконтроллеров

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Архитектура и программирование микроконтроллеров (Шипатов) 2024 (Отсутствуют некоторые файлы, но все лабы вроде на месте) / Labs / Docs / STM / DS12923 STM32H745ZI datasheet.pdf

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STM32H745xI/G	Electrical characteristics

3. Guaranteed by characterization results.

6.3.28Operational amplifier characteristics

Table 109. Operational amplifier characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit

VDDA	Analog supply voltage	-	2	3.3	3.6
VDDA	Range	-	2	3.3	3.6	V
CMIR	Common Mode Input	-	0	-	VDDA	V
	Common Mode Input
	Range
		25°C, no load on output	-	-	±1.5
VIOFFSET	Input offset voltage					mV
VIOFFSET	Input offset voltage	All voltages and	-	-	±2.5	mV
		temperature, no load	-	-	±2.5
		temperature, no load

VIOFFSET	Input offset voltage drift	-	-	±3.0	-	μV/°C
TRIMOFFSETP	Offset trim step at low
TRIMOFFSETP	common input voltage	-	-	1.1	1.5
TRIMLPOFFSETP	common input voltage	-	-	1.1	1.5
TRIMLPOFFSETP	(0.1*VDDA)
	(0.1*VDDA)					mV
TRIMOFFSETN	Offset trim step at high	-	-	1.1	1.5	mV
	Offset trim step at high
	common input voltage
TRIMLPOFFSETN	common input voltage
TRIMLPOFFSETN	(0.9*VDDA)
	(0.9*VDDA)
ILOAD	Drive current	-	-	-	500	μA
ILOAD_PGA	Drive current in PGA mode	-	-	-	270	μA
ILOAD_PGA	Drive current in PGA mode	-	-	-	270
CLOAD	Capacitive load	-	-	-	50	pF
CMRR	Common mode rejection	-	-	80	-	dB
CMRR	ratio	-	-	80	-	dB
	ratio

	Power supply rejection	CLOAD ≤ 50pf /
PSRR	ratio	RLOAD ≥ 4 kΩ(1) at 1 kHz,	50	66	-	dB
		Vcom=VDDA/2
GBW	Gain bandwidth for high	200 mV ≤ Output dynamic	4	7.3	12.3	MHz
GBW	supply range	range ≤ VDDA - 200 mV	4	7.3	12.3	MHz
	supply range	range ≤ VDDA - 200 mV
SR	Slew rate (from 10% and	Normal mode	-	3	-	V/µs
	Slew rate (from 10% and
	90% of output voltage)	High-speed mode	-	30	-
	90% of output voltage)


AO	Open loop gain	200 mV ≤ Output dynamic	59	90	129	dB
AO	Open loop gain	range ≤ VDDA - 200 mV	59	90	129	dB
		range ≤ VDDA - 200 mV
φm	Phase margin	-	-	55	-	°

GM	Gain margin	-	-	12	-	dB

VOHSAT	High saturation voltage	Iload=max or RLOAD=min,	VDDA	-	-
VOHSAT	High saturation voltage	Input at VDDA	−100 mV	-	-
		Input at VDDA	−100 mV			mV
VOLSAT	Low saturation voltage	Iload=max or RLOAD=min,	-	-	100	mV
		Iload=max or RLOAD=min,
		Input at 0 V

DS12923 Rev 1

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Electrical characteristics					STM32H745xI/G

	Table 109. Operational amplifier characteristics (continued)
Symbol	Parameter	Conditions		Min	Typ	Max	Unit

			CLOAD ≤ 50pf,
		Normal	RLOAD ≥ 4 kΩ,	-	0.8	3.2
		mode	follower
tWAKEUP	Wake up time from OFF		configuration				µs
	Wake up time from OFF
	state	High	CLOAD ≤ 50pf,
		speed	RLOAD ≥ 4 kΩ,	-	0.9	2.8
		mode	follower
		mode	configuration
			configuration

		PGA gain = 2		−1	-	1

	Non inverting gain error	PGA gain = 4		−2	-	2
	value	PGA gain = 8		−2.5	-	2.5
		PGA gain = 8		−2.5	-	2.5

		PGA gain = 16		−3	-	3

		PGA gain = 2		−1	-	1

PGA gain	Inverting gain error value	PGA gain = 4		−1	-	1	%

		PGA gain = 8		−2	-	2
		PGA gain = 8		−2	-	2

		PGA gain = 16		−3	-	3

		PGA gain = 2		−1	-	1

	External non-inverting gain	PGA gain = 4		−3	-	3
	error value	PGA gain = 8		−3.5	-	3.5
		PGA gain = 8		−3.5	-	3.5

		PGA gain = 16		−4	-	4

		PGA Gain=2		-	10/10	-
	R2/R1 internal resistance
	R2/R1 internal resistance	PGA Gain=4		-	30/10	-
	values in non-inverting
	values in non-inverting	PGA Gain=8		-	70/10	-
	PGA mode(2)	PGA Gain=8		-	70/10	-
Rnetwork		PGA Gain=16		-	150/10	-	kΩ/
							kΩ/
		PGA Gain = -1		-	10/10	-	kΩ
		PGA Gain = -1		-	10/10	-
	R2/R1 internal resistance
	R2/R1 internal resistance	PGA Gain = -3		-	30/10	-
	values in inverting PGA
	values in inverting PGA	PGA Gain = -7		-	70/10	-
	mode(2)	PGA Gain = -7		-	70/10	-
		PGA Gain = -15		-	150/10	-

Delta R	Resistance variation (R1		-	−15	-	15	%
Delta R	or R2)		-	−15	-	15	%
	or R2)

202/252

DS12923 Rev 1

STM32H745xI/G						Electrical characteristics

	Table 109. Operational amplifier characteristics (continued)
Symbol	Parameter	Conditions			Min		Typ	Max	Unit

				Gain=2	-		GBW/2	-

	PGA bandwidth for			Gain=4	-		GBW/4	-	MHz
	PGA bandwidth for
	different non inverting gain			Gain=8	-		GBW/8	-
	different non inverting gain


PGA BW				Gain=16	-		GBW/16	-

			Gain = -1		-		5.00	-
			Gain = -1		-		5.00	-

	PGA bandwidth for		Gain = -3		-		3.00	-	MHz
	PGA bandwidth for
	different inverting gain		Gain = -7		-		1.50	-
	different inverting gain


			Gain = -15		-		0.80	-

		at			-		140	-
		1 KHz		output loaded	-		140	-	nV/√
en	Voltage noise density	1 KHz

		at		with 4 kΩ	-		55	-	Hz
				with 4 kΩ					Hz

		10 KHz
		10 KHz

		Normal			-		570	1000
		mode		no Load,	-		570	1000
	OPAMP consumption from	mode
IDDA(OPAMP)
		High-		quiescent mode,					µA
	VDDA			quiescent mode,					µA
	VDDA			follower	-		610	1200
		speed		follower	-		610	1200
		mode

1.RLOAD is the resistive load connected to VSSA or to VDDA.

2.R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.

6.3.29Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 110 for DFSDM are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 23: General operating conditions.

•Output speed is set to OSPEEDRy[1:0] = 10

•Capacitive load CL = 30 pF

•Measurement points are done at CMOS levels: 0.5VDD

•VOS level set to VOS1

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).

DS12923 Rev 1

203/252

Electrical characteristics						STM32H745xI/G

			Table 110. DFSDM measured timing 1.62-3.6 V
Symbol	Parameter		Conditions	Min	Typ	Max	Unit

fDFSDMCLK	DFSDM		1.62 < VDD < 3.6 V	-	-	133
fDFSDMCLK	clock		1.62 < VDD < 3.6 V	-	-	133
			SPI mode (SITP[1:0]=0,1),
			External clock mode	-	-	20
			(SPICKSEL[1:0]=0),	-	-	20
			(SPICKSEL[1:0]=0),
			1.62 < VDD < 3.6 V
			SPI mode (SITP[1:0]=0,1),
			External clock mode	-	-	20
			(SPICKSEL[1:0]=0),	-	-	20
			(SPICKSEL[1:0]=0),
fCKIN	Input clock		2.7 < VDD < 3.6 V				MH
(1/TCKIN)	frequency		SPI mode (SITP[1:0]=0,1),				z
			Internal clock mode	-	-	20
			(SPICKSEL[1:0]¹0),	-	-	20
			(SPICKSEL[1:0]¹0),
			1.62 < VDD < 3.6 V
			SPI mode (SITP[1:0]=0,1),
			Internal clock mode	-	-	20
			(SPICKSEL[1:0]¹0),	-	-	20
			(SPICKSEL[1:0]¹0),
			2.7 < VDD < 3.6 V
fCKOUT	Output clock		1.62 < VDD < 3.6 V	-	-	20
fCKOUT	frequency		1.62 < VDD < 3.6 V	-	-	20
DuCyCKOU	Output clock
DuCyCKOU	frequency		1.62 < VDD < 3.6 V	45	50	55	%
T	frequency		1.62 < VDD < 3.6 V	45	50	55	%
T	duty cycle

twh(CKIN)	Input clock		SPI mode (SITP[1:0]=0,1),
	Input clock		External clock mode	TCKIN/2-0.5	TCKIN/2	-
	high and low		External clock mode
twl(CKIN)	high and low		(SPICKSEL[1:0]=0),
twl(CKIN)	time		(SPICKSEL[1:0]=0),
			1.62 < VDD < 3.6 V
			SPI mode (SITP[1:0]=0,1),
tsu	Data input		External clock mode	1.5	-	-
tsu	setup time		(SPICKSEL[1:0]=0),	1.5	-	-
			1.62 < VDD < 3.6 V				ns
			SPI mode (SITP[1:0]=0,1),				ns
			SPI mode (SITP[1:0]=0,1),
th	Data input		External clock mode	0.5	-	-
th	hold time		(SPICKSEL[1:0]=0),	0.5	-	-
			1.62 < VDD < 3.6 V
	Manchester	Manchester mode (SITP[1:0]=2,3),		(CKOUTDIV+1)
TManchester	data period		Internal clock mode	(CKOUTDIV+1)	-	(2*CKOUTDIV)
TManchester	(recovered		(SPICKSEL[1:0]¹0),	* TDFSDMCLK	-	* TDFSDMCLK
	clock period)		1.62 < VDD < 3.6 V

204/252

DS12923 Rev 1

STM32H745xI/G	Electrical characteristics

SPI timing : SPICKSEL = 0

Figure 47. Channel transceiver timing diagrams

CKINy	(SPICKSEL=0)
DFSDM	(SPICKSEL=0)
DFSDM	twl	twh	tr	tf
DATINy	tsu th
DATINy	SITP = 00	tsu	th
	SITP = 00
DFSDM	SITP = 01
	SITP = 01

SPI timing : SPICKSEL = 1, 2, 3

CKOUT	SPICKSEL=3
CKOUT	SPICKSEL=2
DFSDM	SPICKSEL=1

	twl	twh	tr	tf
	tsu th
DATINy	SITP = 0
DATINy		tsu	th
_		tsu	th
_
DFSDM	SITP = 1
DFSDM

Manchester timing

SITP = 2

_DATINy
DFSDM	SITP = 3
	SITP = 3
recovered clock
recovered data 0		0	1	1	0

MS30766V2

DS12923 Rev 1

205/252

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