STM32H745xI/G |
Electrical characteristics |
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6.3.12Memory characteristics
Flash memory
The characteristics are given at TJ = –40 to 125 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased.
Table 61. Flash memory characteristics
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
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Write / Erase 8-bit mode |
- |
6.5 |
- |
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IDD |
Supply current |
Write / Erase 16-bit mode |
- |
11.5 |
- |
mA |
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Write / Erase 32-bit mode |
- |
20 |
- |
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Write / Erase 64-bit mode |
- |
35 |
- |
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Table 62. Flash memory programming (single bank configuration nDBANK=1)
Symbol |
Parameter |
Conditions |
Min(1) |
Typ |
Max(1) |
Unit |
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Program/erase parallelism x 8 |
- |
290 |
580(2) |
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tprog |
Word (266 bits) programming |
Program/erase parallelism x 16 |
- |
180 |
360 |
µs |
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time |
Program/erase parallelism x 32 |
- |
130 |
260 |
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Program/erase parallelism x 64 |
- |
100 |
200 |
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Program/erase parallelism x 8 |
- |
2 |
4 |
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tERASE128KB |
Sector (128 KB) erase time |
Program/erase parallelism x 16 |
- |
1.8 |
3.6 |
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Program/erase parallelism x 32 |
- |
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s |
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Program/erase parallelism x 8 |
- |
13 |
26 |
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tME |
Mass erase time |
Program/erase parallelism x 16 |
- |
8 |
16 |
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Program/erase parallelism x 32 |
- |
6 |
12 |
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Program/erase parallelism x 64 |
- |
5 |
10 |
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Program parallelism x 8 |
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Vprog |
Programming voltage |
Program parallelism x 16 |
1.62 |
- |
3.6 |
V |
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Program parallelism x 32 |
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Program parallelism x 64 |
1.8 |
- |
3.6 |
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1.Guaranteed by characterization results.
2.The maximum programming time is measured after 10K erase operations.
DS12923 Rev 1 |
147/252 |
Electrical characteristics |
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STM32H745xI/G |
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Table 63. Flash memory endurance and data retention |
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Symbol |
Parameter |
Conditions |
Value |
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Unit |
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Min(1) |
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NEND |
Endurance |
TJ = –40 to +125 °C (6 suffix versions) |
10 |
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kcycles |
tRET |
Data retention |
1 kcycle at TA = 85 °C |
30 |
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Years |
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10 kcycles at TA = 55 °C |
20 |
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1. Guaranteed by characterization results.
6.3.13EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
•Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 64. They are based on the EMS levels and classes defined in application note AN1709.
Table 64. EMS characteristics
Symbol |
Parameter |
Conditions |
Level/ |
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Class |
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VFESD |
Voltage limits to be applied on any I/O pin to induce |
VDD = 3.3 V, TA = +25 °C, |
3B |
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a functional disturbance |
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UFBGA240, frcc_c_ck = |
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Fast transient voltage burst limits to be applied |
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400 MHz, conforms to |
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VFTB |
through 100 pF on VDD and VSS pins to induce a |
IEC 61000-4-2 |
5A |
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functional disturbance |
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As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB).
148/252 |
DS12923 Rev 1 |
STM32H745xI/G |
Electrical characteristics |
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Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•Corrupted program counter
•Unexpected reset
•Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.
Table 65. EMI characteristics
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Monitored |
Max vs. |
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Symbol |
Parameter |
Conditions |
[fHSE/fCPU] |
Unit |
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frequency band |
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8/400 MHz |
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0.1 to 30 MHz |
11 |
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VDD = 3.6 V, TA = 25 °C, UFBGA240 package, |
30 to 130 MHz |
6 |
dBµV |
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SEMI |
Peak level |
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130 MHz to 1 GHz |
12 |
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conforming to IEC61967-2 |
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1 GHz to 2 GHz |
7 |
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EMI Level |
2.5 |
- |
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DS12923 Rev 1 |
149/252 |
Electrical characteristics |
STM32H745xI/G |
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6.3.14Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 66. ESD absolute maximum ratings
Symbol |
Ratings |
Conditions |
Packages |
Class |
Maximum |
Unit |
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value(1) |
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Electrostatic discharge |
TA = +25 °C conforming to |
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VESD(HBM) |
voltage (human body |
ANSI/ESDA/JEDEC JS- |
All |
1C |
1000 |
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model) |
001 |
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V |
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Electrostatic discharge |
TA = +25 °C conforming to |
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VESD(CDM) |
voltage (charge device |
ANSI/ESDA/JEDEC JS- |
All |
C1 |
250 |
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model) |
002 |
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1. Guaranteed by characterization results.
Static latchup
Two complementary static tests are required on six parts to assess the latchup performance:
•A supply overvoltage is applied to each power supply pin
•A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 67. Electrical sensitivities
Symbol |
Parameter |
Conditions |
Class |
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LU |
Static latchup class |
TA = +25 °C conforming to JESD78 |
II level A |
150/252 |
DS12923 Rev 1 |