Chapter 4 Hardware Overview
Figure 4-9 shows the relevant timing signals for a typical pretriggered acquisition. The illustration represents five pretrigger and five posttrigger scans, and above-high-level analog triggering is used. See the Analog Trigger Circuit section later in this chapter for more information on analog trigger types.
Start Trigger |
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First Scan |
First Posttrigger Scan |
Scan Clock |
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Scan Counter |
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Terminal Count |
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Stop Trigger |
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End of |
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Acquisition |
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Trigger Level |
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Points Discarded |
Five Pretrigger, Five Posttrigger |
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Points Stored |
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= Discarded Points |
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= Pretrigger Points |
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= Posttrigger Points |
Figure 4-9. Pretrigger Acquisition
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Chapter 4 Hardware Overview
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Table 4-7 describes the pretrigger acquisition signals. |
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Table 4-7. Pretrigger Acquisition Signals |
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Signal |
Description |
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Start Trigger |
Starts data acquisition. In pretrigger mode, the Start Trigger signal |
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enables the storage of pretrigger data. Start Trigger can only be |
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generated through software in pretrigger mode. |
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Scan Clock |
Causes the ADC to convert the input signal into digital data. This signal |
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is also used in the memory controller to write the data into onboard |
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memory. This signal can be generated internally, with a 24-bit down |
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counter clocked with a 20 MHz signal to generate pulses from 20 MHz |
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to 1.19 Hz. The 24-bit counter provides a wide choice of valid |
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frequencies for the Scan Clock signal. In addition, Scan Clock can also |
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be selected from CH0, CH1, TRIG, PFI1, and PFI2, or any of the seven |
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RTSI bus trigger lines. RTSI bus trigger lines are available only on the |
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NI 5102 (PCI, PXI, ISA). |
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Scan Counter |
Is an internally generated signal that pulses once to indicate that the |
Terminal Count |
pretrigger sample count requirement is met. Between the time when |
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this signal pulses and the Stop Trigger occurs, hardware overwrites the |
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oldest points in memory with the most recent points in a circular |
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fashion. All Stop Triggers occurring before Scan Counter Terminal |
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Count are ignored by the device. |
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Stop Trigger |
Terminates the acquisition sequence after acquiring the posttrigger |
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sample count. This trigger can be generated through software, or CH0, |
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CH1, TRIG, PFI1, and PFI2, or any of the seven RTSI bus trigger lines. |
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RTSI bus trigger lines are available only on the NI 5102 (PCI, |
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PXI, ISA). |
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End of Acquisition |
Indicates end of acquisition to the control logic in the hardware. |
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It is generated from a counter that keeps track of points remaining |
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to acquire. It can be exported from the device on the PFI lines. |
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© National Instruments Corporation |
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