
- •NI 5102 User Manual
- •Worldwide Technical Support and Product Information
- •National Instruments Corporate Headquarters
- •Worldwide Offices
- •Important Information
- •Warranty
- •Copyright
- •Trademarks
- •WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS
- •Contents
- •About This Manual
- •Conventions Used in This Manual
- •Related Documentation
- •About Your NI 5102
- •Acquiring Data with Your NI 5102
- •Interactively Controlling your NI 5102 with the Scope Soft Front Panel
- •NI-SCOPE Driver
- •NI Application Software
- •Using PXI with CompactPCI
- •Table 1-1. NI 5102 (PXI) J2 Pin Assignment
- •Optional Equipment
- •What You Need to Get Started
- •Unpacking
- •Installing the NI 5102
- •Table 2-1. NI 5102 (USB) LED Patterns
- •Hardware Configuration
- •Understanding Digitizers
- •Nyquist Theorem
- •Figure 3-1. Aliased Sine Wave When Waveform is Under Sampled
- •Analog Bandwidth
- •Figure 3-2. Analog Bandwidth
- •Sample Rate
- •Figure 3-3. 1 MHz Sine Wave Sample
- •Vertical Sensitivity
- •Figure 3-4. Transfer Function of a 3-Bit ADC
- •ADC Resolution
- •Record Length
- •Triggering Options
- •Making Accurate Measurements
- •Figure 3-5. Dynamic Range of an 8-Bit ADC with Three Different Gain Settings
- •Passive Probe
- •How to Compensate Your Probe
- •Figure 3-7. Connecting the Probe Compensation Cabling
- •Figure 3-8. Probe Compensation Comparison
- •Active and Current Probes
- •Figure 4-1. NI 5102 (PCI, PXI, ISA) Block Diagram
- •Figure 4-2. NI 5102 (PCMCIA, USB) Block Diagram
- •I/O Connector
- •Figure 4-3. NI 5102 (PCI, ISA) I/O Connectors
- •Figure 4-4. NI 5102 (PCMCIA) I/O Connectors
- •Figure 4-6. NI 5102 (PXI) I/O Connectors
- •Signal Connections
- •Table 4-1. I/O Connector Signal Descriptions
- •Serial Communications Port (AUX)
- •Analog Input
- •Table 4-3. AC/DC Coupling Change Settling Rates with NI Probes
- •ADC Pipeline Delay
- •Figure 4-7. Scan Clock Delay
- •Acquisition Modes
- •Posttrigger Acquisition
- •Table 4-4. Possible Number of Samples for Posttriggered Scans
- •Figure 4-8. Posttrigger Acquisition
- •Table 4-5. Posttrigger Acquisition Signals
- •Pretrigger Acquisition
- •Table 4-6. Possible Number of Samples for Pretriggered Mode
- •Figure 4-9. Pretrigger Acquisition
- •Table 4-7. Pretrigger Acquisition Signals
- •Trigger Sources
- •Figure 4-10. Scan Clock, Start Trigger, and Stop Trigger Signal Sources
- •Analog Trigger Circuit
- •Trigger Hold-off
- •Figure 4-11. Pretrigger and Posttrigger Acquisitions with Hold-off
- •Random Interleaved Sampling
- •Calibration
- •RTSI Bus Trigger and Clock Lines
- •Figure 4-12. RTSI Bus Trigger Lines
- •PFI Lines
- •PFI Lines as Inputs
- •PFI Lines as Outputs
- •Master/Slave Operation
- •Restrictions
- •Connecting Devices
- •Glossary
- •Numbers/Symbols
- •Index

Chapter 3 Digitizer Basics
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Probe Adjustment Signal |
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Probe Adjustment Signal |
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Probe Adjustment Signal |
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Proper Amplitude of a |
Reduced Amplitude of a |
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Increased Amplitude of a |
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1 MHz Test Signal |
1 MHz Test Signal |
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1 MHz Test Signal |
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a. Compensated Correctly |
b. Undercompensated |
c. Overcompensated |
Figure 3-8. Probe Compensation Comparison
Active and Current Probes
You can also use active probes and current probes with digitizers and DSOs.
Active probes, such as differential and field-effect transistor (FET) probes, contain active circuitry in the probe itself to reject noise and amplify the signal. FET probes are useful for low-voltage measurements at high frequencies and differential probes are noted for their high common mode rejection ration (CMRR) and nongrounded reference.
Instead of using a series resistance in the loop to measure current, current probes magnetically measure AC and/or DC current flowing in a conductor. This lack of series resistance causes very little interference in the circuit being tested.
© National Instruments Corporation |
3-11 |
NI 5102 User Manual |

4
Hardware Overview
This chapter includes an overview of the NI 5102, explains the operation of each functional unit making up your NI 5102, and describes the signal connections.
Figure 4-1 shows a block diagram of the NI 5102 (PCI, PXI, ISA).
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Channel 0 |
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FIFO |
FIFO |
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Channel 0 |
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Channel 0 |
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8-Bit |
Data |
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DATA(in) |
DATA(out) |
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CH0 |
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20 MS/s |
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FIFO |
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AC/DC Coupling |
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Gain Stage |
CH 0 Out |
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ADC |
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FIFO |
FIFO |
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DATA(out) |
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Channel 1 |
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DATA(in) |
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Data |
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FIFO |
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Channel 1 |
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Channel 1 |
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8-Bit |
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PXI |
CH1 |
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CH 1 Out |
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20 MS/s |
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AC/DC Coupling |
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Gain Stage |
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ISA, PCI, |
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ADC |
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FIFO Controls |
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Gain Control |
Gain and |
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Expansion |
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ADC Control |
DATA |
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Coupling |
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Path |
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Controls |
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PFI1 |
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PFI Module |
Timing |
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FIFO |
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PFI2 |
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Module |
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Control |
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NI 5102 |
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Serial COMM |
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Serial Controls |
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Only |
Serial DACs |
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Expansion |
Expansion Bus Data and Control Signal |
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Analog Trigger |
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Bus Interface |
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Module |
ETS Control |
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RTSI Control |
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EEPROM |
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HTRIGOUT |
LTRIGOUT |
START COUNT |
STOP COUNT |
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RTSI Bus/PXITRIG |
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CH 0 Out |
Analog |
NI 5102 (PCI, ISA) TRIG<0..6>/NI-5102 (PXI) TRIG<0..5> |
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CH 1 Out |
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Trig MUX |
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TRIG |
Trigger |
Trigger |
TRIG_Out |
and Level |
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AC/DC |
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Comparators |
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Coupling |
Amplifier |
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Equivalent |
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Time |
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Sampling |
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Serial |
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Ser |
Communication |
Bus |
AUX 9-Pin DIN |
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PFI2 and Serial Communication |
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NI 5102 (PXI) |
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NI 5102 |
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(PXI)Only |
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Figure 4-1. NI 5102 (PCI, PXI, ISA) Block Diagram
© National Instruments Corporation |
4-1 |
NI 5102 User Manual |