3.4 Options Reference
For optimal use of the optimization and observability tools, -xannotate=yes must be in effect at both compile and link time. Compile and link with -xannotate=no to produce slightly smaller binaries and libraries when optimization and observability tools will not be used.
3.4.113 –xarch=isa
Specify instruction set architecture (ISA).
The following table lists the -xarch keywords common to both SPARC and x86 platforms.
TABLE 14 |
-xarch keywords common to both SPARC and x86 platforms |
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|
Flag |
Meaning |
|
|
generic |
Uses the instruction set common to most processors. This is the default. |
native |
Compile for good performance on this system. The compiler chooses the appropriate setting for |
|
the current system processor it is running on. |
|
|
Note that although -xarch can be used alone, it is part of the expansion of the –xtarget option and may be used to override the -xarch value that is set by a specific -xtarget option. For example:
% f95 -xtarget=T3 -xarch=sparc4 ...
overrides the -xarch set by -xtarget=T3.
This option limits the code generated by the compiler to the instructions of the specified instruction set architecture by allowing only the specified set of instructions. This option does not guarantee use of any target–specific instructions.
If this option is used with optimization, the appropriate choice can provide good performance of the executable on the specified architecture. An inappropriate choice results in a binary program that is not executable on the intended target platform.
Note the following:
■Object binary files (.o) compiled with generic,sparc, sparcvis2, sparcvis3, sparcfmaf, sparcima can be linked and can execute together, but can only run on a processor supporting all the instruction sets linked.
■For any particular choice, the generated executable might not run or run much more slowly on legacy architectures. Also, because quad-precision (REAL*16 and long double) floating-
106 Oracle Developer Studio 12.6: Fortran User's Guide • July 2017
3.4 Options Reference
point instructions are not implemented in any of these instruction set architectures, the compiler does not use these instructions in the code it generates.
The default when -xarch is not specified is generic.
Table 15, “-xarch Values for SPARC Platforms,” on page 107 gives details for each of the - xarch keywords on SPARC platforms.
TABLE 15 |
-xarch Values for SPARC Platforms |
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|
|
-xarch= |
|
Meaning (SPARC) |
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|
|
sparc |
|
Compile for the SPARC–V9 ISA. Compile for the V9 ISA, but without the Visual Instruction |
|
|
Set (VIS), and without other implementation-specific ISA extensions. This option enables the |
|
|
compiler to generate code for good performance on the V9 ISA. |
|
|
|
sparc4 |
|
Compile for the SPARC4 version of the SPARCV9 ISA. |
|
|
Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the |
|
|
UltraSPARC extensions, which includes VIS 1.0, the UltraSPARC-III extensions, which includes |
|
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VIS2.0, the fused floating-point multiply-add instructions, VIS 3.0, and SPARC4 instructions. |
|
|
|
sparc4b |
|
Compile for the SPARC4B version of the SPARC-V9 ISA. Enables the compiler to use |
|
|
instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, which includes |
|
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VIS 1.0, the UltraSPARC-III extensions, which includes VIS2.0, the SPARC64 VI extensions |
|
|
for floating-point multiply-add, the SPARC64 VII extensions for integer multiply-add, and the |
|
|
PAUSE and CBCOND instructions from the SPARC T4 extensions. |
|
|
|
sparc4c |
|
Compile for the SPARC4C version of the SPARC-V9 ISA. Enables the compiler to use |
|
|
instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, which includes |
|
|
VIS 1.0, the UltraSPARC-III extensions, which includes VIS2.0, the SPARC64 VI extensions for |
|
|
floating-point multiply-add, the SPARC64 VII extensions for integer multiply-add, the VIS3B |
|
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subset of the VIS 3.0 instructions a subset of the SPARC T3 extensions, called the VIS3B subset |
|
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of VIS 3.0, and the PAUSE and CBCOND instructions from the SPARC T4 extensions. |
|
|
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sparc5 |
|
Compile for the SPARC5 version of the SPARC-V9 ISA. Enables the compiler to use instructions |
|
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from the SPARC-V9 instruction set, plus the extensions, which includes VIS 1.0, the Ultra |
|
|
SPARC-III extensions, which includes VIS2.0, the fused floating-point multiply-add instructions, |
|
|
VIS 3.0, SPARC4, and SPARC5 instructions. |
|
|
|
sparcvis |
|
Compile for the SPARC–V9 ISA with UltraSPARC extensions. Compile for SPARC-V9 plus the |
|
|
Visual Instruction Set (VIS) version 1.0, and with UltraSPARC extensions. This option enables |
|
|
the compiler to generate code for good performance on the UltraSPARC architecture. |
|
|
|
sparcvis2 |
|
Compile for the SPARC-V9 ISA with UltraSPARC-III extensions. Enables the compiler to |
|
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generate object code for the UltraSPARC architecture, plus the Visual Instruction Set (VIS) |
|
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version 2.0, and with UltraSPARC III extensions. |
|
|
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sparcvis3 |
|
Compile for the SPARC VIS version 3 of the SPARC-V9 ISA. Enables the compiler to use |
|
|
instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the |
|
|
Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual |
|
|
Instruction Set (VIS) version 2.0, the fused multiply-add instructions, and the Visual Instruction |
|
|
Set (VIS) version 3.0 |
|
|
|
sparcfmaf |
|
Compile for the sparcfmaf version of the SPARC-V9 ISA. Enables the compiler to use |
|
|
instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the |
|
|
Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual |
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3.4 Options Reference
-xarch= |
Meaning (SPARC) |
|
|
|
Instruction Set (VIS) version 2.0, and the SPARC64 VI extensions for floating-point multiply- |
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add. |
|
Note that you must use -xarch=sparcfmafin conjunction with -fma=fused and some |
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optimization level to get the compiler to attempt to find opportunities to use the multiply-add |
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instructions automatically. |
|
|
sparcace |
Compile for the sparcace version of the SPARC-V9 ISA. Enables the compiler to use |
|
instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the |
|
Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual |
|
Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, |
|
the SPARC64 VII extensions for integer multiply-add, and the SPARC64 X extensions for ACE |
|
floating-point. |
|
|
sparcaceplus |
Compile for the sparcaceplus version of the SPARC-V9 ISA. Enables the compiler to use |
|
instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the |
|
Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual |
|
Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, the |
|
SPARC64 VII extensions for integer multiply-add, the SPARC64 X extensions for SPARCACE |
|
floating-point, and the SPARC64 X+ extensions for SPARCACE floating-point. |
|
|
sparcace2 |
Compile for the sparcace2 version of the SPARC-V9 ISA. Enables the compiler to use |
|
instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the |
|
Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual |
|
Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, the |
|
SPARC64 VII extensions for integer multiply-add, the SPARC64 X extensions for SPARCACE |
|
floating-point, the SPARC64 X+ extensions for SPARCACE floating-point, and the SPARC64 |
|
XII extensions for SPARCACE floating-point. |
|
|
sparcima |
Compile for the sparcima version of the SPARC-V9 ISA. Enables the compiler to use |
|
instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the |
|
Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual |
|
Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, |
|
and the SPARC64 VII extensions for integer multiply-add. |
|
|
v9 |
Equivalent to -m64 -xarch=sparc |
|
Legacy makefiles and scripts that use -xarch=v9 to obtain the 64-bit data type model need only |
|
use -m64. |
|
|
v9a |
Equivalent to -m64 -xarch=sparcvis and is provided for compatibility with earlier releases. |
|
|
v9b |
Equivalent to -m64 -xarch=sparcvis2 and is provided for compatibility with earlier releases. |
|
|
Table 16, “-xarch Values for x86 Platforms,” on page 108 details each of the -xarch keywords on x86 platforms. The default on x86 is generic if -xarch is not specified.
TABLE 16 |
-xarch Values for x86 Platforms |
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|
|
|
-xarch= |
|
Meaning (x86) |
|
|
|
386 (Obsolete) |
|
You should not use this option. Use -xarch=generic instead. |
|
|
For a complete list of obsolete options, see “3.3.4 Obsolete Option |
|
|
Flags” on page 53. |
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3.4 Options Reference |
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-xarch= |
Meaning (x86) |
|
|
|
|
pentium_pro (Obsolete) |
You should not use this option. Use -xarch=generic instead. |
|
|
For a complete list of obsolete options, see “3.3.4 Obsolete Option |
|
|
Flags” on page 53. |
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|
|
pentium_proa |
Adds the AMD extensions (3DNow!, 3DNow! extensions, and MMX extensions) to |
|
|
the 32-bit Pentium Pro architecture. |
|
|
|
|
sse (Obsolete) |
You should not use this option. Use -xarch=generic instead. |
|
|
For a complete list of obsolete options, see “3.3.4 Obsolete Option |
|
|
Flags” on page 53. |
|
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|
|
ssea |
Adds the AMD extensions (3DNow!, 3DNow! extensions, and MMX extensions) to |
|
|
the 32-bit SSE architecture. |
|
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sse2 |
Adds the SSE2 instruction set to the pentium_pro. (See Note below.) |
|
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sse2a |
Adds the AMD extensions (3DNow!, 3DNow! extensions, and MMX extensions) to |
|
|
the 32-bit SSE2 architecture. |
|
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sse3 |
Adds the SSE3 instruction set to the SSE2 instruction set. |
|
|
|
|
sse3a |
Adds the AMD extended instructions including 3dnow to the SSE3 instruction set. |
|
|
|
|
sse3a |
Adds AMD extended instructions, including 3DNow! to the SSE3 instruction set. |
|
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|
ssse3 |
Adds the SSSE3 instructions to the SSE3 instruction set. |
|
|
|
|
sse4_1 |
Adds the SSE4.1 instructions to the SSSE3 instruction set. |
|
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|
|
sse4_2 |
Adds the SSE4.2 instructions to the SSE4.1 instruction set. |
|
|
|
|
amdsse4a |
Adds the SSE4a instructions to the AMD instruction set. |
|
|
|
|
aes |
Adds the Intel Advanced Encryption Standard instruction set. Note that the compiler |
|
|
does not generate AES instructions automatically when -xarch=aes is specified unless |
|
|
the source code includes .il inline code, _asm statements, or assembler code that use |
|
|
AES instructions, or references to AES intrinsic functions. |
|
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avx |
Uses Intel Advanced Vector Extensions instruction set. |
|
|
|
|
avx_i |
Uses Intel Advanced Vector Extensions instruction set with the RDRND, FSGSBASE |
|
|
and F16C instruction sets. |
|
|
|
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avx2 |
Uses Intel Advanced Vector Extensions 2 instruction set. |
|
|
|
|
avx2_i |
Supplements the pentium_pro, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, |
|
|
AVX2 instruction sets with Broadwell instructions (ADOX, ADCX, MULX, RDSEED, |
|
|
PREFETCHWT1). |
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|
avx512 |
Uses the instructions sets AVX512F, AVX512CDI, AVX512VLI, AVX512BW and |
|
|
AVX512DQ. |
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3.4.113.1 Special Cautions for x86/x64 Platforms:
There are some important considerations when compiling for Oracle Solaris x86 platforms.
Chapter 3 • Fortran Compiler Options |
109 |