29 On-Chip Sensors and Analog Signal Processing

Register 29.23. SENS_SAR_DAC_CTRL2_REG (0x009c)

SENS_DAC_CW_EN2 1: selects CW generator as source for PDAC2_DAC[7:0], 0: selects register reg_pdac2_dac[7:0] as source for PDAC2_DAC[7:0]. (R/W)

SENS_DAC_CW_EN1 1: selects CW generator as source for PDAC1_DAC[7:0], 0: selects register reg_pdac1_dac[7:0] as source for PDAC1_DAC[7:0]. (R/W)

SENS_DAC_INV2 DAC2, 00: does not invert any bits, 01: inverts all bits, 10: inverts MSB, 11: inverts all bits except for MSB. (R/W)

SENS_DAC_INV1 DAC1, 00: does not invert any bits, 01: inverts all bits, 10: inverts MSB, 11: inverts all bits except for MSB. (R/W)

SENS_DAC_SCALE2 DAC2, 00: no scale; 01: scale to 1/2; 10: scale to 1/4; 11: scale to 1/8. (R/W)

SENS_DAC_SCALE1 DAC1, 00: no scale; 01: scale to 1/2; 10: scale to 1/4; 11: scale to 1/8. (R/W)

SENS_DAC_DC2 DC offset for DAC2 CW generator. (R/W)

SENS_DAC_DC1 DC offset for DAC1 CW generator. (R/W)

29.6.2 Advanced Peripheral Bus

The addresses in parenthesis besides register names are the register addresses relative to the base address of 0x6000_2600 (by AHB bus). The absolute register addresses are listed in Section 29.5.2 Advanced Peripheral Bus.

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Register 29.24. APB_SARADC_CTRL_REG (0x10)

APB_SARADC_DATA_SAR_SEL 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case, the resolution should not contain more than 11 bits; 0: using 12-bit SAR ADC resolution. (R/W)

APB_SARADC_SAR2_PATT_P_CLEAR Clears the pointer of pattern table for DIG ADC2 CTRL. (R/W)

APB_SARADC_SAR1_PATT_P_CLEAR Clears the pointer of pattern table for DIG ADC1 CTRL. (R/W)

APB_SARADC_SAR2_PATT_LEN SAR ADC2, 0 - 15 means pattern table length of 1 - 16. (R/W)

APB_SARADC_SAR1_PATT_LEN SAR ADC1, 0 - 15 means pattern table length of 1 - 16. (R/W)

APB_SARADC_SAR_CLK_DIV SAR clock divider. (R/W)

APB_SARADC_SAR_CLK_GATED Reserved. Please initialize to 0b1 (R/W)

APB_SARADC_SAR_SEL 0: SAR1, 1: SAR2, this setting is applicable in the single SAR mode. (R/W)

APB_SARADC_WORK_MODE 0: single mode, 1: double mode, 2: alternate mode. (R/W)

APB_SARADC_SAR2_MUX 1: SAR ADC2 is controlled by DIG ADC2 CTRL, 0: SAR ADC2 is controlled by PWDET CTRL. (R/W)

APB_SARADC_START Reserved. Please initialize to 0 (R/W)

APB_SARADC_START_FORCE Reserved. Please initialize to 0 (R/W)

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Register 29.25. APB_SARADC_CTRL2_REG (0x14)

APB_SARADC_SAR2_INV 1: data to DIG ADC2 CTRL is inverted, 0: data is not inverted. (R/W)

APB_SARADC_SAR1_INV 1: data to DIG ADC1 CTRL is inverted, 0: data is not inverted. (R/W)

APB_SARADC_MAX_MEAS_NUM Max conversion number. (R/W)

APB_SARADC_MEAS_NUM_LIMIT Reserved. Please initialize to 0b1 (R/W)

Register 29.26. APB_SARADC_FSM_REG (0x18)

Register 29.27. APB_SARADC_SAR1_PATT_TAB1_REG (0x1C)

APB_SARADC_SAR1_PATT_TAB1_REG Pattern tables 0 - 3 for SAR ADC1, one byte for each pattern table: [31:28] pattern0_channel, [27:26] pattern0_bit_width, [25:24] pattern0_attenuation, [23:20] pattern1_channel, etc. (R/W)

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Register 29.28. APB_SARADC_SAR1_PATT_TAB2_REG (0x20)

APB_SARADC_SAR1_PATT_TAB2_REG Pattern tables 4 - 7 for SAR ADC1, one byte for each pattern table: [31:28] pattern4_channel, [27:26] pattern4_bit_width, [25:24] pattern4_attenuation, [23:20] pattern5_channel, etc. (R/W)

Register 29.29. APB_SARADC_SAR1_PATT_TAB3_REG (0x24)

APB_SARADC_SAR1_PATT_TAB3_REG Pattern tables 8 - 11 for SAR ADC1, one byte for each pattern table: [31:28] pattern8_channel, [27:26] pattern8_bit_width, [25:24] pattern8_attenuation, [23:20] pattern9_channel, etc. (R/W)

Register 29.30. APB_SARADC_SAR1_PATT_TAB4_REG (0x28)

APB_SARADC_SAR1_PATT_TAB4_REG Pattern tables 12 - 15 for SAR ADC1, one byte for each pattern table: [31:28] pattern12_channel, [27:26] pattern12_bit_width, [25:24] pattern12_attenuation, [23:20] pattern13_channel, etc. (R/W)

Register 29.31. APB_SARADC_SAR2_PATT_TAB1_REG (0x2C)

APB_SARADC_SAR2_PATT_TAB1_REG Pattern tables 0 - 3 for SAR ADC2, one byte for each pattern table: [31:28] pattern0_channel, [27:26] pattern0_bit_width, [25:24] pattern0_attenuation, [23:20] pattern1_channel, etc. (R/W)

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Register 29.32. APB_SARADC_SAR2_PATT_TAB2_REG (0x30)

APB_SARADC_SAR2_PATT_TAB2_REG Pattern tables 4 - 7 for SAR ADC2, one byte for each pattern table: [31:28] pattern4_channel, [27:26] pattern4_bit_width, [25:24] pattern4_attenuation, [23:20] pattern5_channel, etc. (R/W)

Register 29.33. APB_SARADC_SAR2_PATT_TAB3_REG (0x34)

APB_SARADC_SAR2_PATT_TAB3_REG Pattern tables 8 - 11 for SAR ADC2, one byte for each pattern table: [31:28] pattern8_channel, [27:26] pattern8_bit_width, [25:24] pattern8_attenuation, [23:20] pattern9_channel, etc. (R/W)

Register 29.34. APB_SARADC_SAR2_PATT_TAB4_REG (0x38)

APB_SARADC_SAR2_PATT_TAB4_REG Pattern tables 12 - 15 for SAR ADC2, one byte for each pattern table: [31:28] pattern12_channel, [27:26] pattern12_bit_width, [25:24] pattern12_attenuation, [23:20] pattern13_channel, etc. (R/W)

29.6.3 RTC I/O

For details, please refer to Section Registers in Chapter IO_MUX and GPIO Matrix.

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