3 Reset and Clock

3.2.6RTC Clock

The clock sources of RTC_SLOW_CLK and RTC_FAST_CLK are low-frequency clocks. The RTC module can operate when most other clocks are stopped.

RTC_SLOW_CLK is used to clock the Power Management module. It can be sourced from RC_SLOW_CLK, XTL32K_CLK or RC_FAST_DIV_CLK.

RTC_FAST_CLK is used to clock the On-chip Sensor module. It can be sourced from a divided XTL_CLK or from RC_FAST_CLK.

3.2.7Audio PLL

The operation of audio and other time-critical data-transfer applications requires highly-configurable, low-jitter, and accurate clock sources. The clock sources derived from system clocks that serve digital peripherals may carry jitter and, therefore, they do not support a high-precision clock frequency setting.

Providing an integrated precision clock source can minimize system cost. To this end, ESP32 integrates an audio PLL. The Audio PLL formula is as follows:

fout = fxtal(sdm2 + sdm128 + sdm0216 + 4)

2(odiv + 2)

The parameters of this formula are defined below:

•fxtal: the frequency of the crystal oscillator, usually 40 MHz;

•sdm0: the value is 0 ~ 255;

•sdm1: the value is 0 ~ 255;

•sdm2: the value is 0 ~ 63;

•odiv: the value is 0 ~ 31;

The operating frequency range of the numerator is 350 MHz ~ 500 MHz:

Please note that sdm1 and sdm0 are not available on revision0 of ESP32. Please consult the silicon revision in

ECO and Workarounds for Bugs in ESP32 for further details.

Audio PLL can be manually enabled or disabled via registers RTC_CNTL_PLLA_FORCE_PU and RTC_CNTL_PLLA _FORCE_PD, respectively. Disabling it takes priority over enabling it. When RTC_CNTL_PLLA_FORCE_PU and RTC_CNTL_PLLA_FORCE_PD are 0, PLL will follow the state of the system, i.e., when the system enters sleep mode, PLL will be disabled automatically; when the system wakes up, PLL will be enabled automatically.

3.3Register Summary

The addresses in this section are relative to the SYSCON base address provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory.

Submit Documentation Feedback

3 Reset and Clock

3.4Registers

The addresses in this section are relative to the SYSCON base address provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory.

Register 3.1. SYSCON_SYSCLK_CONF_REG (0x0000)

SYSCON_PRE_DIV_CNT Configures the divider value of CPU_CLK when the source of CPU_CLK is XTL_CLK or RC_FAST_CLK. The value range is 0x0 ~ 0x3FF. CPU_CLK = XTL_CLK ( or RC_FAST_CLK) / (the value of this field +1). (R/W)

Register 3.2. SYSCON_XTAL_TICK_CONF_REG (0x0004)

SYSCON_XTAL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK is XTL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1). (R/W)

Submit Documentation Feedback

3 Reset and Clock

Register 3.3. SYSCON_PLL_TICK_CONF_REG (0x0008)

SYSCON_PLL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK is PLL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1).

(R/W)

Register 3.4. SYSCON_CK8M_TICK_CONF_REG (0x000C)

SYSCON_CK8M_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK is FOSC_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1). (R/W)

Register 3.5. SYSCON_APLL_TICK_CONF_REG (0x003C)

SYSCON_APLL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK is APLL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1). (R/W)

Submit Documentation Feedback

3 Reset and Clock

Register 3.6. SYSCON_DATE_REG (0x007C)

SYSCON_DATE Chip revision register. For more information see ESP32 Series SoC Errata. (R/W)

Submit Documentation Feedback