15 Remote Control Peripheral (RMT)

15 Remote Control Peripheral (RMT)

15.1Introduction

The RMT (Remote Control) module is primarily designed to send and receive infrared remote control signals that implement on-off keying in a carrier frequency, but due to its design it can be used to generate various types of signals. An RMT transmitter does this by reading consecutive duration values of an active and inactive output from the built-in RAM block, optionally modulating it with a carrier wave. A receiver will inspect its input signal, optionally filtering it, and will place the lengths of time the signal is active and inactive in the RAM block.

The RMT module has eight channels, numbered zero to seven; registers, signals and blocks that are duplicated in each channel are indicated by an n which is used as a placeholder for the channel number.

15.2Functional Description

15.2.1 RMT Architecture

Figure 15­1. RMT Architecture

The RMT module contains eight channels. Each channel has both a transmitter and a receiver, but only one of them can be active in every channel. The eight channels share a 512x32-bit RAM block which can be read and written by the processor cores over the APB bus, read by the transmitters, and written by the receivers. The transmitted signal can optionally be modulated by a carrier wave. Each channel is clocked by a divided-down signal derived from either the APB bus clock or REF_TICK.

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15 Remote Control Peripheral (RMT)

15.2.2 RMT RAM

Figure 15­2. Data Structure

The data structure in RAM is shown in Figure 15-2. Each 32-bit value contains two 16-bit entries, with two fields in every entry, ”level” and ”period”. ”Level” indicates whether a high-/low-level value was received or is going to be sent, while ”period” points out the divider-clock cycles for which the level lasts. A zero period is interpreted as an end-marker: the transmitter will stop transmitting once it has read this, and the receiver will write this, once it has detected that the signal it received has gone idle.

Normally, only one block of 64x32-bit worth of data can be sent or received. If the data size is larger than this block size, blocks can be extended or the channel can be configured for the wraparound mode.

The RMT RAM can be accessed via the APB bus. The initial address is 0x3FF56800. The RAM block is divided into eight 64x32-bit blocks. By default, each channel uses one block (block zero for channel zero, block one for channel one, and so on). Users can extend the memory to a specific channel by configuring the RMT_MEM_SIZE_CHn register; setting this to >1 will prompt the channel to use the memory of subsequent channels as well. The RAM address range of channel n is start_addr_CHn to end_addr_CHn, which is defined by:

start_addr_chn = 0x3FF56800 + 64 4 n, and

end_addr_chn = 0x3FF56800 + (64 4 n + 64 4 RMT_MEM_SIZE_CHn)mod(512 4) − 4

To protect a receiver from overwriting the blocks a transmitter is about to transmit, RMT_MEM_OWNER_CHn can be configured to designate the owner, be it a transmitter or receiver, of channel n’s RAM block. This way, if this ownership is violated, the RMT_CHn_ERR interrupt will be generated.

Note: When enabling the continuous transmission mode by setting RMT_REG_TX_CONTI_MODE, the transmitter will transmit the data on the channel continuously, that is, from the first byte to the last one, then from the first to the last again, and so on. In this mode, there will be an idle level lasting one clk_div cycle between N and N+1 transmissions.

15.2.3 Clock

The main clock of a channel is generated by taking either the 80 MHz APB clock or REF_TICK (usually 1MHz), according to the state of RMT_REF_ALWAYS_ON_CHn. (For more information on clock sources, please see Chapter Reset And Clock.) Then, the aforementioned state gets scaled down using a configurable 8-bit divider to create the channel clock which is used by both the carrier wave generator and the counter. The divider value can be set by configuring RMT_DIV_CNT_CHn.

15.2.4 Transmitter

When the RMT_TX_START_CHn register is 1, the transmitter of channel n will start reading and sending data from RAM. The transmitter will receive a 32-bit value each time it reads from RAM. Of these 32 bits, the low 16-bit entry is sent first and the high entry second.

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