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13 UART Controller (UART)

13.3.6 AT_CMD Character Structure

Figure 13­4. AT_CMD Character Format

Figure 13-4 shows a special AT_CMD character format. If the receiver constantly receives UART_AT_CMD_CHAR characters and these characters satisfy the following conditions, interrupt UART_AT_CMD_CHAR_DET_INT will be generated.

Between the first UART_AT_CMD_CHAR and the last non-UART_AT_CMD_CHAR, there are at least UART_ PER_IDLE_NUM APB clock cycles.

Between every UART_AT_CMD_CHAR character there must be less than UART_RX_GAP_TOUT APB clock cycles.

The number of received UART_AT_CMD_CHAR characters must be equal to, or greater than, UART_CHAR_NUM.

Between the last UART_AT_CMD_CHAR character received and the next non-UART_AT_CMD_CHAR, there are at least UART_POST_IDLE_NUM APB clock cycles.

13.3.7 Flow Control

UART controller supports both hardware and software flow control. Hardware flow control regulates data flow through input signal dsrn_in and output signal rtsn_out. Software flow control regulates data flow by inserting special characters in the flow of sent data and by detecting special characters in the flow of received data.

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13 UART Controller (UART)

13.3.7.1 Hardware Flow Control

Figure 13­5. Hardware Flow Control

Figure 13-5 illustrates how the UART hardware flow control works. In hardware flow control, a high state of the output signal rtsn_out signifies that a data transmission is requested, while a low state of the same signal notifies the counterpart to stop data transmission until rtsn_out is pulled high again. There are two ways for a transmitter to realize hardware flow control:

UART_RX_FLOW_EN is 0: The level of rtsn_out can be changed by configuring UART_SW_RTS.

UART_RX_FLOW_EN is 1: If data in Rx_FIFO is greater than UART_RX_FLOW_THRHD, the level of rtsn_out will be lowered.

If the UART controller detects an edge on ctsn_in, it will generate interrupt UART_CTS_CHG_INT and will stop transmitting data, once the current data transmission is completed.

The high level of the output signal dtrn_out signifies that the transmitter has finished data preparation. UART controller will generate interrupt UART_DSR_CHG_INT, after it detects an edge on the input signal dsrn_in. After the software detects the above-mentioned interrupt, the input signal level of dsrn_in can be figured out by reading UART_DSRN. The software then decides whether it is able to receive data at that time or not.

Setting UART_LOOPBACK will enable the UART loopback detection function. In this mode, the output signal txd_out of UART is connected to its input signal rxd_in, rtsn_out is connected to ctsn_in, and dtrn_out is connected to dsrn_out. If the data transmitted corresponds to the data received, UART is able to transmit and receive data normally.

13.3.7.2 Software Flow Control

Software can force the transmitter to stop transmitting data by setting UART_FORCE_XOFF, as well as force the transmitter to continue sending data by setting UART_FORCE_XON.

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13 UART Controller (UART)

UART can also control the software flow by transmitting special characters. Setting UART_SW_FLOW_CON_EN will enable the software flow control function. If the number of data bytes that UART has received exceeds that of the UART_XOFF threshold, the UART controller can send UART_XOFF_CHAR to instruct its counterpart to stop data transmission.

When UART_SW_FLOW_CON_EN is 1, software can send flow control characters at any time. When UART_SEND _XOFF is set, the transmitter will insert a UART_XOFF_CHAR and send it after the current data transmission is completed. When UART_SEND_XON is set, the transmitter will insert a UART_XON_CHAR and send it after the current data transmission is completed.

13.3.8 UART DMA

For information on the UART DMA, please refer to Chapter DMA Controller.

13.3.9 UART Interrupts

UART_AT_CMD_CHAR_DET_INT: Triggered when the receiver detects the configured at_cmd char.

UART_RS485_CLASH_INT: Triggered when a collision is detected between transmitter and receiver in RS485 mode.

UART_RS485_FRM_ERR_INT: Triggered when a data frame error is detected in RS-485.

UART_RS485_PARITY_ERR_INT: Triggered when a parity error is detected in RS-485 mode.

UART_TX_DONE_INT: Triggered when the transmitter has sent out all FIFO data.

UART_TX_BRK_IDLE_DONE_INT: Triggered when the transmitter’s idle state has been kept to a minimum after sending the last data.

UART_TX_BRK_DONE_INT: Triggered when the transmitter completes sending NULL characters, after all data in transmit-FIFO are sent.

UART_GLITCH_DET_INT: Triggered when the receiver detects a START bit.

UART_SW_XOFF_INT: Triggered, if the receiver gets an Xon char when UART_SW_FLOW_CON_EN is set to 1.

UART_SW_XON_INT: Triggered, if the receiver gets an Xoff char when UART_SW_FLOW_CON_EN is set to 1.

UART_RXFIFO_TOUT_INT: Triggered when the receiver takes more time than RX_TOUT_THRHD to receive a byte.

UART_BRK_DET_INT: Triggered when the receiver detects a NULL character (i.e. logic 0 for one NULL character transmission) after stop bits.

UART_CTS_CHG_INT: Triggered when the receiver detects an edge change of the CTSn signal.

UART_DSR_CHG_INT: Triggered when the receiver detects an edge change of the DSRn signal.

UART_RXFIFO_OVF_INT: Triggered when the receiver gets more data than the FIFO can store.

UART_FRM_ERR_INT: Triggered when the receiver detects a data frame error .

UART_PARITY_ERR_INT: Triggered when the receiver detects a parity error in the data.

UART_TXFIFO_EMPTY_INT: Triggered when the amount of data in the transmit-FIFO is less than what tx_mem_cnttxfifo_cnt specifies.

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