12 I2S Controller (I2S)

12 I2S Controller (I2S)

12.1Overview

The I2S bus provides a flexible communication interface for streaming digital data in multimedia applications, especially digital audio applications. The ESP32 includes two I2S interfaces: I2S0 and I2S1.

The I2S standard bus defines three signals: a clock signal, a channel selection signal, and a serial data signal. A basic I2S data bus has one master and one slave. The roles remain unchanged throughout the communication. The I2S modules on the ESP32 provide separate transmit and receive channels for high performance.

Figure 12­1. I2S System Block Diagram

Figure 12-1 is the system block diagram of the ESP32 I2S module. In the figure above, the value of ”n” can be either 0 or 1. There are two independent I2S modules embedded in ESP32, namely I2S0 and I2S1. Each I2S module contains a Tx (transmit) unit and a Rx (receive) unit. Both the Tx unit and the Rx unit have a three-wire interface that includes a clock line, a channel selection line and a serial data line. The serial data line of the Tx unit is fixed as output, and the serial data line of the Rx unit is fixed as input. The clock line and the channel selection line of the Tx and Rx units can be configured to both master transmitting mode and slave receiving mode. In the LCD mode, the serial data line extends to the parallel data bus. Both the Tx unit and the Rx unit have a 32-bit-wide FIFO with a depth of 64. Besides, only I2S0 supports on-chip DAC/ADC modes, as well as receiving and transmitting PDM signals.

The right side of Figure 12-1 shows the signal bus of the I2S module. The signal naming rule of the Rx and Tx units is I2SnA_B_C, where ”n” stands for either I2S0 or I2S1; ”A” represents the direction of I2S module’s data bus signal, ”I” represents input, ”O” represents output; ”B” represents signal function; ”C” represents the signal direction, ”in” means that the signal is input into the I2S module, while ”out” means that the I2S module outputs the signal. For a detailed description of the I2S signal bus, please refer to Table 12-1. Table 12-1 describes the signal bus of the I2S module. Except for the I2Sn_CLK signal, all other signals are mapped to the chip pin via the

Submit Documentation Feedback

12 I2S Controller (I2S)

GPIO matrix and IO MUX. The I2Sn_CLK signal is mapped to the chip pin via the IO_MUX. For details, please refer to the chapter about IO_MUX and the GPIO Matrix.

Table 12­1. I2S Signal Bus Description

Note:

1.Assume that the bit width of the input/output signal is N, the input signal should be configured to I2SnI_Data_in[N- 1:0], and the output signal to I2SnO_Data_out[23:23-N+1]. Generally, for input signals, N=8 or 16; while for output signals, N=8, 16 or 24 (note that I2S1 does not support 24-bit width).

2.I2Sn_CLK can only be mapped to GPIO0, U0RXD (GPIO3) or U0TXD (GPIO1) by selecting GPIO functions CLK_OUT1, CLK_OUT2, or CLK_OUT3. For more information, see Table 4-3: IO_MUX Pad List.

12.2Features

I2S mode

•Configurable high-precision output clock

•Full-duplex and half-duplex data transmit and receive modes

•Supports multiple digital audio standards

•Embedded A-law compression/decompression module

•Configurable clock signal

Submit Documentation Feedback

12I2S Controller (I2S)

•Supports PDM signal input and output

•Configurable data transmit and receive modes LCD mode

•Supports multiple LCD modes, including external LCD

•Supports external Camera

•Supports on-chip DAC/ADC modes

I2S interrupts

•Standard I2S interface interrupts

•I2S DMA interface interrupts

12.3The Clock of I2S Module

As is shown in Figure 12-2, I2Sn_CLK, as the master clock of I2S module, is derived from the 160 MHz clock PLL_F160M_CLK or the configurable analog PLL output clock APLL_CLK. The serial clock (BCK) of the I2S module is derived from I2Sn_CLK. The I2S_CLKA_ENA bit of register I2S_CLKM_CONF_REG is used to select either PLL_F160M_CLK or APLL_CLK as the clock source for I2Sn. PLL_F160_CLK is used as the clock source for I2Sn, by default.

Notice:

•When using PLL_F160M_CLK as the clock source, it is not recommended to divide it using decimals. For high performance audio applications, the analog PLL output clock source APLL_CLK must be used to acquire highly accurate I2Sn_CLK and BCK. For further details, please refer to the chapter entitled Reset and Clock.

•When ESP32 I2S works in slave mode, the master must use I2Sn_CLK as the master clock and fi2s >= 8 *

fBCK.

Figure 12­2. I2S Clock

The relation between I2Sn_CLK frequency fi2s and the divider clock source frequency fpll can be seen in the equation below:

fpll fi2s = N + ba

”N”, whose value is >=2, corresponds to the REG _CLKM_DIV_NUM [7:0] bits of register I2S_CLKM_CONF_REG , ”b” is the I2S_CLKM_DIV_B[5:0] bit and ”a” is the I2S_CLKM_DIV_A[5:0] bit.

In master mode, the serial clock BCK in the I2S module is derived from I2Sn_CLK, that is:

fi2s fBCK = M

Submit Documentation Feedback