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11 I2C Controller (I2C)

Figure 11­12. Master Reads from Slave with 7­bit Address in Three Segments

11.3.7 Interrupts

I2C_TX_SEND_EMPTY_INT: Triggered when the Master or Slave has sent nonfifo_tx_thres bytes of data.

I2C_RX_REC_FULL_INT: Triggered when the Master or Slave has received nonfifo_rx_thres bytes of data.

I2C_ACK_ERR_INT: Triggered when the Master receives an ACK that is not as expected, or when the Slave receives an ACK whose value is 1.

I2C_TRANS_START_INT: Triggered when the Master or Slave sends the START bit.

I2C_TIME_OUT_INT: Triggered when the SCL stays high or low for more than I2C_TIME_OUT clocks.

I2C_TRANS_COMPLETE_INT: Triggered when the Master or Slave detects a STOP bit.

I2C_MASTER_TRAN_COMP_INT: Triggered when the Master sends or receives a byte.

I2C_ARBITRATION_LOST_INT: Triggered when the Master’s SCL is high, while the output value and input value of the SDA do not match.

I2C_END_DETECT_INT: Triggered when the Master deals with the END command.

Espressif Systems

294

ESP32 TRM (Version 5.0)

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