8 SDIO Slave Controller

Register 8.35. SLCHOST_CONF_REG (0x1F0)

SLCHOST_HSPEED_CON_EN Set this bit and HINF_HIGHSPEED_ENABLE, then set the EHS (Enable High-Speed) bit in CCCR at the Host side to output the corresponding signal at the rising clock edge. (R/W)

SLCHOST_FRC_POS_SAMP Set this bit to sample the corresponding signal at the rising clock edge. (R/W)

SLCHOST_FRC_NEG_SAMP Set this bit to sample the corresponding signal at the falling clock edge. (R/W)

SLCHOST_FRC_SDIO20 Set this bit to output the corresponding signal at the rising clock edge. (R/W)

SLCHOST_FRC_SDIO11 Set this bit to output the corresponding signal at the falling clock edge. (R/W)

8.7HINF Registers

The addresses in parenthesis besides register names are the register addresses relative to the SDIO Slave base address (0x3FF4_B000) provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 8.4 Register Summary.

Register 8.36. HINF_CFG_DATA1_REG (0x4)

HINF_HIGHSPEED_ENABLE Please initialize to 1. Do not modify it. (R/W)

HINF_SDIO_IOREADY1 Please initialize to 1. Do not modify it. (R/W)

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