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Национальный исследовательский университет «МИЭТ»

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Интерфейсы вычислительных систем

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8 SDIO Slave Controller

																																REPLACE
																																_
																																NO
																																_
																																TOKEN
																																_
															(reserved)																	SLC0
															(reserved)																SLC
																																_

31																														1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

SLC_SLC0_TOKEN_NO_REPLACE Please initialize to 1. Do not modify it. (R/W)

											MORE	WDATA
										INC		WDATA
											_
										_		_
	(reserved)				(reserved)				LEN			LEN
	(reserved)				(reserved)			SLC0		(reserved)		SLC0
									_			_

31	29	28					23	22	21	20	19		0
														Reset

	0x0	0	0	0	0	0	0	0	0	0		0x000000

SLC0_LEN_INC_MORE Set this bit to add the value of SLC0_LEN to that of SLC0_LEN_WDATA. (WO)

SLC0_LEN_WDATA The packet length sent. (WO)

	(reserved)		LEN
	(reserved)		SLC0
			_

31	20	19		0
					Reset

	0x0000		0x000000

SLC0_LEN Indicates the packet length sent by the Slave. (RO)

8.6SLC Host Registers

The addresses in parenthesis besides register names are the register addresses relative to the SDIO Slave base address (0x3FF5_5000) provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 8.4 Register Summary.

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8 SDIO Slave Controller

			TOKEN1
			_
			SLC0
			_
	(reserved)		HOSTREG		(reserved)
31	28	27	16	15		0
							Reset

	0x000		0x000		0x000

HOSTREG_SLC0_TOKEN1 The accumulated number of Slave’s receiving buffers. (RO)

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8 SDIO Slave Controller

INT

RAW

PACKET

RAW

INT

NEW

OVF

UDF

_ SLC0

(reserved)

(reserved) SLC0HOST

(reserved)

SLC0HOSTSLC0HOST

(reserved)

RAW

INT

_ BIT7

_ BIT6

_ BIT5

_ BIT4

_ BIT3

_ BIT2

_ BIT1

_ BIT0

TOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOST

_ SLC0

SLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOST

31	26	25	24	23	22				18	17	16	15							8	7	6	5	4	3	2	1	0
																												Reset

0x00		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

SLC0HOST_SLC0_RX_NEW_PACKET_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (RO)
SLC0HOST_SLC0_TX_OVF_INT_RAW The	raw	interrupt		status	bit	for	the
SLC0HOST_SLC0_TX_OVF_INT interrupt. (RO)
SLC0HOST_SLC0_RX_UDF_INT_RAW The	raw	interrupt		status	bit	for	the
SLC0HOST_SLC0_RX_UDF_INT interrupt. (RO)
SLC0HOST_SLC0_TOHOST_BIT7_INT_RAW The		raw	interrupt	status	bit	for	the
SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (RO)
SLC0HOST_SLC0_TOHOST_BIT6_INT_RAW The		raw	interrupt	status	bit	for	the
SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (RO)
SLC0HOST_SLC0_TOHOST_BIT5_INT_RAW The		raw	interrupt	status	bit	for	the
SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (RO)
SLC0HOST_SLC0_TOHOST_BIT4_INT_RAW The		raw	interrupt	status	bit	for	the
SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO)
SLC0HOST_SLC0_TOHOST_BIT3_INT_RAW The		raw	interrupt	status	bit	for	the
SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO)
SLC0HOST_SLC0_TOHOST_BIT2_INT_RAW The		raw	interrupt	status	bit	for	the
SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO)
SLC0HOST_SLC0_TOHOST_BIT1_INT_RAW The		raw	interrupt	status	bit	for	the
SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO)
SLC0HOST_SLC0_TOHOST_BIT0_INT_RAW The		raw	interrupt	status	bit	for	the
SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO)

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8 SDIO Slave Controller

INT

_ PACKET

INT

_ BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

NEW

OVF

UDF

TOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOST

_ SLC0

SLC0

_ SLC0

SLC0

_ SLC0

(reserved)

SLC0HOST

(reserved)

SLC0HOSTSLC0HOST

(reserved)

SLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOST

Reset

0x00

SLC0HOST_SLC0_RX_NEW_PACKET_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (RO)

SLC0HOST_SLC0_TX_OVF_INT_ST

The

masked

interrupt

status

bit

for

the

SLC0HOST_SLC0_TX_OVF_INT interrupt. (RO)

SLC0HOST_SLC0_RX_UDF_INT_ST

The

masked

interrupt

status

bit

for

the

SLC0HOST_SLC0_RX_UDF_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT7_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT6_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT5_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT4_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT3_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT2_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT1_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT0_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO)

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8 SDIO Slave Controller

			CHECK
		_		LEN
	LEN			LEN
	_			_
	SLC0			SLC0
	_			_
	HOSTREG			HOSTREG
	_			_
	SLCHOST			SLCHOST
31	20		19		0
						Reset

	0x000			0x000
	SLCHOST_HOSTREG_SLC0_LEN_CHECK Its value			is HOSTREG_SLC0_LEN[9:0]	plus
	HOSTREG_SLC0_LEN[19:10]. (RO)

SLCHOST_HOSTREG_SLC0_LEN The accumulated value of the data length sent by the Slave. The value gets updated only when the Host reads it.

	CONF3		CONF2		CONF1		CONF0
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF3 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF2 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF1 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF0 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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8 SDIO Slave Controller

	CONF7		CONF6		CONF5		CONF4
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF7 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF6 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF5 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF4 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

	CONF11		CONF10		CONF9		CONF8
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF11 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF10 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF9 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF8 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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	CONF15		CONF14
	_		_
	SLCHOST		SLCHOST
31	24	23	16
				Reset

	0x000		0x000

SLCHOST_CONF15 The information interaction register between Host and Slave. Both Host and Slave can be read from and written to this. (R/W)

SLCHOST_CONF14 The information interaction register between Host and Slave. Both Host and Slave can be read from and written to this. (R/W)

	CONF19		CONF18
	_		_
	SLCHOST		SLCHOST
31	24	23	16
				Reset

	0x000		0x000

SLCHOST_CONF19 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF18 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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8 SDIO Slave Controller

	CONF27		CONF26		CONF25		CONF24
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF27 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF26 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF25 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF24 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

						CONF31										CONF29
					_										_
				SLCHOST				(reserved)						SLCHOST					(reserved)
31							24	23	16	15							8	7		0
																					Reset

0	0	0	0	0	0	0	0	0x000		0	0	0	0	0	0	0	0		0x000

SLCHOST_CONF31 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared automatically. (WO)

SLCHOST_CONF29 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared automatically. (WO)

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ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

	CONF35		CONF34		CONF33		CONF32
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF35 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF34 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF33 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF32 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

	CONF39		CONF38		CONF37		CONF36
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF39 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF38 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF37 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF36 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

	CONF43		CONF42		CONF41		CONF40
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF43 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF42 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF41 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF40 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

	CONF47		CONF46		CONF45		CONF44
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF47 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF46 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF45 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF44 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

	CONF51		CONF50		CONF49		CONF48
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF51 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF50 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF49 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF48 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

	CONF55		CONF54		CONF53		CONF52
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF55 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF54 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF53 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF52 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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8 SDIO Slave Controller

	CONF59		CONF58		CONF57		CONF56
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF59 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF58 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF57 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF56 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

	CONF63		CONF62		CONF61		CONF60
	_		_		_		_
	SLCHOST		SLCHOST		SLCHOST		SLCHOST
31	24	23	16	15	8	7		0
									Reset

	0x000		0x000		0x000		0x000

SLCHOST_CONF63 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF62 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF61 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF60 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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8 SDIO Slave Controller

INT

CLR

_ PACKET

CLR

_ INT

INT

_ BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

NEW

OVF

UDF

TOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOST

_ SLC0

SLC0

_ SLC0

(reserved)

SLC0HOST

(reserved)

SLC0HOSTSLC0HOST

(reserved)

SLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOST

Reset

0x00

SLC0HOST_SLC0_RX_NEW_PACKET_INT_CLR Set

this

bit

clear

the

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (WO)

SLC0HOST_SLC0_TX_OVF_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TX_OVF_INT interrupt. (WO)

SLC0HOST_SLC0_RX_UDF_INT_CLR Set this bit to clear the SLC0HOST_SLC0_RX_UDF_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT7_INT_CLR Set	this	bit	to	clear	the
SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (WO)
SLC0HOST_SLC0_TOHOST_BIT6_INT_CLR Set	this	bit	to	clear	the
SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (WO)
SLC0HOST_SLC0_TOHOST_BIT5_INT_CLR Set	this	bit	to	clear	the
SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (WO)
SLC0HOST_SLC0_TOHOST_BIT4_INT_CLR Set	this	bit	to	clear	the
SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (WO)
SLC0HOST_SLC0_TOHOST_BIT3_INT_CLR Set	this	bit	to	clear	the
SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (WO)
SLC0HOST_SLC0_TOHOST_BIT2_INT_CLR Set	this	bit	to	clear	the
SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (WO)
SLC0HOST_SLC0_TOHOST_BIT1_INT_CLR Set	this	bit	to	clear	the
SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (WO)
SLC0HOST_SLC0_TOHOST_BIT0_INT_CLR Set	this	bit	to	clear	the
SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (WO)

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8 SDIO Slave Controller

INT

ENA

_ PACKET

ENA

INT

_ BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

NEW

OVF

UDF

TOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOST

SLC0

_ FN1

FN1

(reserved)

SLC0HOST

(reserved)

SLC0HOSTSLC0HOST

(reserved)

SLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOST

Reset

0x00

SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TX_OVF_INT_ENA The

interrupt

enable

bit

for

the

SLC0HOST_FN1_SLC0_TX_OVF_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_RX_UDF_INT_ENA The

interrupt

enable

bit

for

the

SLC0HOST_FN1_SLC0_RX_UDF_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT interrupt. (R/W)

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