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8 SDIO Slave Controller

Register 8.11. SLC_RX_DSCR_CONF_REG (0x98)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REPLACE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TOKEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(reserved)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SLC_SLC0_TOKEN_NO_REPLACE Please initialize to 1. Do not modify it. (R/W)

Register 8.12. SLC0_LEN_CONF_REG (0xE4)

 

 

 

 

 

 

 

 

 

 

 

 

MORE

WDATA

 

 

 

 

 

 

 

 

 

 

 

 

 

INC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

_

 

 

 

(reserved)

 

 

 

(reserved)

 

 

LEN

 

LEN

 

 

 

 

 

 

 

SLC0

(reserved)

SLC0

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

29

 

28

 

 

 

 

23

22

21

20

19

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x0

 

0

0

0

0

0

0

0

0

0

 

0x000000

 

SLC0_LEN_INC_MORE Set this bit to add the value of SLC0_LEN to that of SLC0_LEN_WDATA. (WO)

SLC0_LEN_WDATA The packet length sent. (WO)

Register 8.13. SLC0_LENGTH_REG (0xE8)

 

(reserved)

 

LEN

 

 

 

 

SLC0

 

 

 

 

 

_

 

 

 

 

 

 

 

 

31

20

19

 

0

 

 

 

 

 

 

Reset

 

 

 

 

 

 

0x0000

 

0x000000

 

SLC0_LEN Indicates the packet length sent by the Slave. (RO)

8.6SLC Host Registers

The addresses in parenthesis besides register names are the register addresses relative to the SDIO Slave base address (0x3FF5_5000) provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 8.4 Register Summary.

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8 SDIO Slave Controller

Register 8.14. SLC0HOST_TOKEN_RDATA (0x44)

 

 

 

TOKEN1

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

SLC0

 

 

 

 

 

 

 

_

 

 

 

 

 

(reserved)

 

HOSTREG

 

(reserved)

 

 

31

28

27

16

15

 

0

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

HOSTREG_SLC0_TOKEN1 The accumulated number of Slave’s receiving buffers. (RO)

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8 SDIO Slave Controller

Register 8.15. SLC0HOST_INT_RAW_REG (0x50)

 

 

 

 

 

 

 

 

 

 

INT

_

RAW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PACKET

_

 

 

 

 

 

 

 

 

 

 

 

 

RAW

 

RAW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

 

 

INT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

INT

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NEW

 

 

 

 

 

 

 

 

 

OVF

_

 

UDF

_

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

_

 

_

 

 

 

 

 

 

 

 

RX

 

 

 

 

 

 

 

 

TX

 

 

RX

 

 

 

 

 

 

 

 

 

_ SLC0

_

 

 

 

 

 

 

 

_ SLC0

_

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ SLC0

 

 

 

 

 

 

 

 

 

 

 

(reserved)

(reserved) SLC0HOST

 

 

(reserved)

 

 

SLC0HOSTSLC0HOST

 

 

 

 

 

 

 

 

 

 

 

 

 

(reserved)

 

 

 

 

 

 

 

_

RAW

_

RAW

_

RAW

_

RAW

_

RAW

_

RAW

_

RAW

_

RAW

 

 

 

 

 

 

INT

 

 

INT

 

 

INT

 

 

INT

 

 

INT

 

 

INT

 

 

INT

 

 

INT

 

 

 

 

 

 

_

 

 

_

 

 

_

 

 

_

 

 

_

 

 

_

 

 

_

 

 

_

 

 

 

 

 

_ BIT7

_ BIT6

_ BIT5

_ BIT4

_ BIT3

_ BIT2

_ BIT1

_ BIT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

TOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOST

 

 

 

 

 

 

 

_ SLC0

 

_

_

 

 

_

 

 

_

 

 

_

 

 

_

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

_ SLC0

_ SLC0

_ SLC0

 

_ SLC0

 

_ SLC0

 

_ SLC0

 

_ SLC0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

26

25

24

23

22

 

 

 

18

17

16

15

 

 

 

 

 

 

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x00

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SLC0HOST_SLC0_RX_NEW_PACKET_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (RO)

 

 

 

 

 

SLC0HOST_SLC0_TX_OVF_INT_RAW The

raw

interrupt

status

bit

for

the

SLC0HOST_SLC0_TX_OVF_INT interrupt. (RO)

 

 

 

 

 

 

SLC0HOST_SLC0_RX_UDF_INT_RAW The

raw

interrupt

status

bit

for

the

SLC0HOST_SLC0_RX_UDF_INT interrupt. (RO)

 

 

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT7_INT_RAW The

raw

interrupt

status

bit

for

the

SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (RO)

 

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT6_INT_RAW The

raw

interrupt

status

bit

for

the

SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (RO)

 

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT5_INT_RAW The

raw

interrupt

status

bit

for

the

SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (RO)

 

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT4_INT_RAW The

raw

interrupt

status

bit

for

the

SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO)

 

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT3_INT_RAW The

raw

interrupt

status

bit

for

the

SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO)

 

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT2_INT_RAW The

raw

interrupt

status

bit

for

the

SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO)

 

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT1_INT_RAW The

raw

interrupt

status

bit

for

the

SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO)

 

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT0_INT_RAW The

raw

interrupt

status

bit

for

the

SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO)

 

 

 

 

 

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8 SDIO Slave Controller

Register 8.16. SLC0HOST_INT_ST_REG (0x58)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

_

ST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ST

 

 

 

 

ST

 

 

 

 

ST

 

 

 

 

ST

 

 

 

ST

 

 

 

ST

 

 

 

ST

 

 

 

ST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ PACKET

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

_

 

INT

_

 

INT

_

 

INT

_

 

INT

_

 

INT

_

 

INT

_

 

INT

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

_

ST

 

INT

_

 

 

 

 

 

 

 

 

 

 

 

_ BIT7

_

BIT6

_

BIT5

_

BIT4

_

BIT3

_

BIT2

_

BIT1

_

BIT0

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

_

_

_

_

_

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NEW

 

 

 

 

 

 

 

 

 

 

 

OVF

_

 

 

UDF

_

 

 

 

 

 

 

 

 

 

 

 

TOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RX

_

 

 

 

 

 

 

 

 

 

TX

_

RX

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ SLC0

_

 

 

 

 

 

 

 

 

 

_ SLC0

_

 

SLC0

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ SLC0

_

_ SLC0

_

SLC0

_

_ SLC0

_

_ SLC0

_

_ SLC0

_

_ SLC0

_

_ SLC0

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(reserved)

 

 

(reserved)

SLC0HOST

 

 

 

 

(reserved)

 

 

 

SLC0HOSTSLC0HOST

 

 

 

 

 

 

 

 

 

 

 

 

(reserved)

 

 

 

 

SLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

26

25

24

 

23

22

 

 

 

 

 

 

 

18

 

17

16

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

7

6

5

 

 

4

 

3

 

 

 

 

2

 

 

 

 

1

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x00

 

0

0

 

0

0

0

 

 

 

0

0

 

0

 

0

0

 

0

 

 

0

 

 

 

0

 

 

0

0

0

0

0

 

0

0

0

 

 

0

 

0

 

 

 

0

 

 

 

0

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_SLC0_RX_NEW_PACKET_INT_ST The masked interrupt status bit for the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (RO)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_SLC0_TX_OVF_INT_ST

 

The

 

masked

 

 

 

 

 

interrupt

 

 

status

 

 

 

bit

 

 

 

 

for

 

 

 

 

 

 

the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_SLC0_TX_OVF_INT interrupt. (RO)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_SLC0_RX_UDF_INT_ST

 

The

 

 

masked

 

 

 

 

interrupt

 

status

 

 

 

bit

 

 

 

 

 

for

 

 

 

 

 

 

the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_SLC0_RX_UDF_INT interrupt. (RO)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT7_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT6_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT5_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT4_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT3_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT2_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT1_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT0_INT_ST The masked interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO)

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Register 8.17. SLCHOST_PKT_LEN_REG (0x60)

 

 

 

CHECK

 

 

 

 

 

_

LEN

 

 

 

LEN

 

 

 

_

 

 

_

 

 

 

SLC0

 

 

SLC0

 

 

 

_

 

 

_

 

 

 

HOSTREG

 

 

HOSTREG

 

 

 

_

 

 

_

 

 

 

SLCHOST

 

 

SLCHOST

 

 

31

20

 

19

 

0

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

0x000

 

 

0x000

 

 

SLCHOST_HOSTREG_SLC0_LEN_CHECK Its value

is HOSTREG_SLC0_LEN[9:0]

plus

 

HOSTREG_SLC0_LEN[19:10]. (RO)

 

 

 

SLCHOST_HOSTREG_SLC0_LEN The accumulated value of the data length sent by the Slave. The value gets updated only when the Host reads it.

Register 8.18. SLCHOST_CONF_W0_REG (0x6C)

 

CONF3

 

CONF2

 

CONF1

 

CONF0

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF3 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF2 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF1 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF0 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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Register 8.19. SLCHOST_CONF_W1_REG (0x70)

 

CONF7

 

CONF6

 

CONF5

 

CONF4

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF7 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF6 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF5 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF4 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

Register 8.20. SLCHOST_CONF_W2_REG (0x74)

 

CONF11

 

CONF10

 

CONF9

 

CONF8

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF11 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF10 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF9 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF8 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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Register 8.21. SLCHOST_CONF_W3_REG (0x78)

 

CONF15

 

CONF14

 

 

_

 

_

 

 

SLCHOST

 

SLCHOST

 

31

24

23

16

 

 

 

 

 

Reset

 

 

 

 

 

0x000

 

0x000

SLCHOST_CONF15 The information interaction register between Host and Slave. Both Host and Slave can be read from and written to this. (R/W)

SLCHOST_CONF14 The information interaction register between Host and Slave. Both Host and Slave can be read from and written to this. (R/W)

Register 8.22. SLCHOST_CONF_W4_REG (0x7C)

 

CONF19

 

CONF18

 

 

_

 

_

 

 

SLCHOST

 

SLCHOST

 

31

24

23

16

 

 

 

 

 

Reset

 

 

 

 

 

0x000

 

0x000

SLCHOST_CONF19 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF18 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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Register 8.23. SLCHOST_CONF_W6_REG (0x88)

 

CONF27

 

CONF26

 

CONF25

 

CONF24

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF27 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF26 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF25 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF24 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

Register 8.24. SLCHOST_CONF_W7_REG (0x8C)

 

 

 

 

 

 

CONF31

 

 

 

 

 

 

 

 

CONF29

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

SLCHOST

 

 

(reserved)

 

 

 

 

 

SLCHOST

 

 

 

(reserved)

 

 

31

 

 

 

 

 

 

24

23

16

15

 

 

 

 

 

 

8

7

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

0

0

0x000

 

0

0

0

0

0

0

0

0

 

0x000

 

SLCHOST_CONF31 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared automatically. (WO)

SLCHOST_CONF29 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared automatically. (WO)

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Register 8.25. SLCHOST_CONF_W8_REG (0x9C)

 

CONF35

 

CONF34

 

CONF33

 

CONF32

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF35 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF34 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF33 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF32 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

Register 8.26. SLCHOST_CONF_W9_REG (0xA0)

 

CONF39

 

CONF38

 

CONF37

 

CONF36

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF39 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF38 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF37 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF36 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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Register 8.27. SLCHOST_CONF_W10_REG (0xA4)

 

CONF43

 

CONF42

 

CONF41

 

CONF40

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF43 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF42 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF41 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF40 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

Register 8.28. SLCHOST_CONF_W11_REG (0xA8)

 

CONF47

 

CONF46

 

CONF45

 

CONF44

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF47 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF46 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF45 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF44 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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Register 8.29. SLCHOST_CONF_W12_REG (0xAC)

 

CONF51

 

CONF50

 

CONF49

 

CONF48

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF51 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF50 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF49 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF48 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

Register 8.30. SLCHOST_CONF_W13_REG (0xB0)

 

CONF55

 

CONF54

 

CONF53

 

CONF52

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF55 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF54 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF53 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF52 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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Register 8.31. SLCHOST_CONF_W14_REG (0xB4)

 

CONF59

 

CONF58

 

CONF57

 

CONF56

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF59 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF58 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF57 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF56 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

Register 8.32. SLCHOST_CONF_W15_REG (0xB8)

 

CONF63

 

CONF62

 

CONF61

 

CONF60

 

 

 

_

 

_

 

_

 

_

 

 

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

SLCHOST

 

 

31

24

23

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

0x000

 

0x000

 

0x000

 

0x000

 

SLCHOST_CONF63 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF62 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF61 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

SLCHOST_CONF60 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W)

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Register 8.33. SLC0HOST_INT_CLR_REG (0xD4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

_

CLR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLR

 

 

CLR

 

 

CLR

 

 

CLR

 

 

CLR

 

 

CLR

 

 

CLR

 

 

CLR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ PACKET

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLR

 

 

CLR

 

 

 

 

 

 

 

 

 

 

 

 

_ INT

_

 

 

INT

_

 

 

INT

_

 

 

INT

_

 

 

INT

_

 

 

INT

_

 

 

INT

_

 

 

INT

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

_

INT

_

 

 

 

 

 

 

 

 

 

 

 

_ BIT7

BIT6

_

BIT5

_

BIT4

_

BIT3

_

BIT2

_

BIT1

_

BIT0

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

_

 

_

 

_

 

_

 

_

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NEW

 

 

 

 

 

 

 

 

 

 

 

OVF

_

 

 

UDF

_

 

 

 

 

 

 

 

 

 

 

 

TOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RX

_

 

 

 

 

 

 

 

 

 

TX

_

RX

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ SLC0

_

 

 

 

 

 

 

 

 

 

_ SLC0

_

 

SLC0

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ SLC0

_

_ SLC0

_

 

_

 

 

 

_

_ SLC0

_

_ SLC0

_

_ SLC0

_

_ SLC0

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ SLC0

_ SLC0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(reserved)

 

 

(reserved)

SLC0HOST

 

 

 

 

(reserved)

 

 

 

SLC0HOSTSLC0HOST

 

 

 

 

 

 

 

 

 

 

 

 

(reserved)

 

 

 

SLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

26

25

24

 

23

22

 

 

 

 

 

 

 

18

 

17

16

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

7

6

 

5

 

 

4

 

3

 

 

 

2

 

 

 

1

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x00

 

0

0

 

0

0

0

 

 

 

0

0

 

0

 

0

0

 

0

 

 

0

 

 

 

0

 

 

0

0

0

0

0

0

0

 

0

 

 

0

 

0

 

 

0

 

 

0

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_SLC0_RX_NEW_PACKET_INT_CLR Set

 

 

 

 

 

this

 

 

bit

 

 

to

 

 

 

 

clear

 

 

 

 

 

 

the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (WO)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_SLC0_TX_OVF_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TX_OVF_INT interrupt. (WO)

SLC0HOST_SLC0_RX_UDF_INT_CLR Set this bit to clear the SLC0HOST_SLC0_RX_UDF_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT7_INT_CLR Set

this

bit

to

clear

the

SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (WO)

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT6_INT_CLR Set

this

bit

to

clear

the

SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (WO)

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT5_INT_CLR Set

this

bit

to

clear

the

SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (WO)

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT4_INT_CLR Set

this

bit

to

clear

the

SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (WO)

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT3_INT_CLR Set

this

bit

to

clear

the

SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (WO)

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT2_INT_CLR Set

this

bit

to

clear

the

SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (WO)

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT1_INT_CLR Set

this

bit

to

clear

the

SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (WO)

 

 

 

 

SLC0HOST_SLC0_TOHOST_BIT0_INT_CLR Set

this

bit

to

clear

the

SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (WO)

 

 

 

 

Espressif Systems

188

ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

Register 8.34. SLC0HOST_FUNC1_INT_ENA_REG (0xDC)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

_

ENA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ENA

 

 

ENA

 

 

ENA

 

 

ENA

 

 

 

ENA

 

 

ENA

 

 

ENA

 

 

ENA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ PACKET

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ENA

 

 

ENA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

_

 

 

 

INT

_

 

 

 

INT

_

 

 

INT

_

 

 

 

INT

_

 

 

INT

_

 

 

INT

_

 

 

INT

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

_

INT

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ BIT7

 

_

BIT6

 

_

BIT5

 

_

BIT4

_

BIT3

_

 

BIT2

_

BIT1

_

BIT0

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

_

 

 

_

 

_

 

 

_

 

_

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NEW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OVF

_

 

 

UDF

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOSTTOHOST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RX

_

 

 

 

 

 

 

 

 

 

 

 

 

TX

_

RX

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0

_

 

 

 

 

 

 

 

 

 

 

 

SLC0

_

 

 

SLC0

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0

_

 

SLC0

 

_

SLC0

 

_

SLC0

 

_

SLC0

 

_

SLC0

_

SLC0

_

 

SLC0

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

 

 

 

 

 

 

 

 

 

_

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

_

 

_

 

_

 

_

 

_

_

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ FN1

 

 

 

 

 

 

 

 

 

 

 

_ FN1

 

_ FN1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ FN1

_ FN1

_ FN1

_ FN1

 

 

FN1

 

 

FN1

 

 

FN1

 

 

FN1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_

 

 

_

 

 

_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(reserved)

 

 

(reserved)

SLC0HOST

 

 

 

 

(reserved)

 

 

 

SLC0HOSTSLC0HOST

 

 

 

 

 

 

 

 

 

 

 

 

 

(reserved)

 

 

 

SLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOSTSLC0HOST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

26

25

24

 

23

22

 

 

 

 

 

 

 

18

 

17

 

16

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

7

6

 

5

 

 

4

 

 

 

3

 

 

2

 

 

 

1

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x00

 

0

0

 

0

0

0

 

 

0

 

0

0

 

0

 

0

0

 

 

0

 

 

 

0

 

 

 

 

0

 

 

 

0

0

0

0

0

0

 

0

 

 

0

 

 

0

 

 

0

 

 

 

0

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA The interrupt enable bit for the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT interrupt. (R/W)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_FN1_SLC0_TX_OVF_INT_ENA The

 

 

 

 

 

 

interrupt

 

 

enable

 

 

 

bit

 

 

 

 

 

 

for

 

 

 

 

 

 

 

 

the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_FN1_SLC0_TX_OVF_INT interrupt. (R/W)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_FN1_SLC0_RX_UDF_INT_ENA The

 

 

 

 

 

 

 

interrupt

 

 

enable

 

 

 

 

bit

 

 

 

 

 

 

for

 

 

 

 

 

 

 

the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_FN1_SLC0_RX_UDF_INT interrupt. (R/W)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT interrupt. (R/W)

Espressif Systems

189

ESP32 TRM (Version 5.0)

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