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Национальный исследовательский университет «МИЭТ»

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Интерфейсы вычислительных систем

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8SDIO Slave Controller

•SLC0INT_SLC0_RX_EOF_INT Slave sending operation is finished.

•SLC0INT_SLC0_RX_DONE_INT A single buffer is sent by Slave.

•SLC0INT_SLC0_TX_SUC_EOF_INT Slave receiving operation is finished.

•SLC0INT_SLC0_TX_DONE_INT A single buffer is finished during receiving operation.

•SLC0INT_SLC0_TX_OVF_INT Slave receiving buffer overflow interrupt.

•SLC0INT_SLC0_RX_UDF_INT Slave sending buffer underflow interrupt.

•SLC0INT_SLC0_TX_START_INT Slave receiving interrupt initialization.

•SLC0INT_SLC0_RX_START_INT Slave sending interrupt initialization.

•SLC0INT_SLC_FRHOST_BITn_INT (n: 0 ~ 7) Host interrupts Slave.

8.4Register Summary

	Name	Description		Address		Access
	SDIO DMA (SLC) configuration registers

	SLCCONF0_REG	SLCCONF0_SLC configuration		0x3FF58000		R/W

	SLC0RX_LINK_REG	Transmitting linked list configuration		0x3FF5803C		R/W

	SLC0TX_LINK_REG	Receiving linked list configuration		0x3FF58040		R/W

	SLCINTVEC_TOHOST_REG	Interrupt sector for Slave to interrupt Host		0x3FF5804C		WO

	SLC0TOKEN1_REG	Number of receiving buffer		0x3FF58054		WO

	SLCCONF1_REG	Control register		0x3FF58060		R/W

	SLC_RX_DSCR_CONF_REG	DMA transmission configuration		0x3FF58098		R/W

	SLC0_LEN_CONF_REG	Length control of the transmitting packets		0x3FF580E4		R/W

	SLC0_LENGTH_REG	Length of the transmitting packets		0x3FF580E8		R/W

	Interrupt Registers

	SLC0INT_RAW_REG	Raw interrupt status		0x3FF58004		RO

	SLC0INT_ST_REG	Interrupt status		0x3FF58008		RO

	SLC0INT_ENA_REG	Interrupt enable		0x3FF5800C		R/W

	SLC0INT_CLR_REG	Interrupt clear		0x3FF58010		WO


	Name		Description		Address		Access
	SDIO SLC Host registers

	SLC0HOST_TOKEN_RDATA		The accumulated number of Slave’s receiving				RO
	SLC0HOST_TOKEN_RDATA		buffers		0x3FF55044		RO
			buffers

	SLCHOST_PKT_LEN_REG		Length of the transmitting packets		0x3FF55060		RO

	SLCHOST_CONF_W0_REG		Host and Slave communication register0		0x3FF5506C		R/W

	SLCHOST_CONF_W1_REG		Host and Slave communication register1		0x3FF55070		R/W

	SLCHOST_CONF_W2_REG		Host and Slave communication register2		0x3FF55074		R/W

	SLCHOST_CONF_W3_REG		Host and Slave communication register3		0x3FF55078		R/W

	SLCHOST_CONF_W4_REG		Host and Slave communication register4		0x3FF5507C		R/W

	SLCHOST_CONF_W6_REG		Host and Slave communication register6		0x3FF55088		R/W

	SLCHOST_CONF_W7_REG		Interrupt vector for Host to interrupt Slave		0x3FF5508C		WO

	SLCHOST_CONF_W8_REG		Host and Slave communication register8		0x3FF5509C		R/W

Espressif Systems		166		ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

SLCHOST_CONF_W9_REG		Host and Slave communication register9		0x3FF550A0		R/W

SLCHOST_CONF_W10_REG		Host and Slave communication register10		0x3FF550A4		R/W

SLCHOST_CONF_W11_REG		Host and Slave communication register11		0x3FF550A8		R/W

SLCHOST_CONF_W12_REG		Host and Slave communication register12		0x3FF550AC		R/W

SLCHOST_CONF_W13_REG		Host and Slave communication register13		0x3FF550B0		R/W

SLCHOST_CONF_W14_REG		Host and Slave communication register14		0x3FF550B4		R/W

SLCHOST_CONF_W15_REG		Host and Slave communication register15		0x3FF550B8		R/W

SLCHOST_CONF_REG		Edge configuration		0x3FF551F0		R/W

Interrupt Registers

SLC0HOST_INT_RAW_REG		Raw interrupt		0x3FF55000		RO

SLC0HOST_INT_ST_REG		Masked interrupt status		0x3FF55058		RO

SLC0HOST_INT_CLR_REG		Interrupt clear		0x3FF550D4		WO

SLC0HOST_FUNC1_INT_ENA_REG		Interrupt enable		0x3FF550DC		R/W


Name	Description		Address		Access
SDIO HINF registers

HINF_CFG_DATA1_REG	SDIO specification configuration		0x3FF4B004		R/W

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ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

8.5SLC Registers

The addresses in parenthesis besides register names are the register addresses relative to the SDIO Slave base address (0x3FF5_8000) provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 8.4 Register Summary.

																							CLR										WRBACKTESTTEST
																							_
																						AUTO										_			_		RST RST
																						_						RX	AUTOLOOPLOOP							RX	RST RST
																					TOKEN							RX		RX			TX			RX		TX
																												_			_		_			_		_
																					_							_	_			_				_	_
																				SLC0							SLC0SLC0SLC0								SLC0SLC0
																			_								_	_	_						_	_
								(reserved)									SLCCONF0				(reserved)				SLCCONF0SLCCONF0SLCCONF0(reserved)SLCCONF0SLCCONF0
31																15	14	13						7	6	5	4	3	2			1		0
																																			Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	0	0		0			0

SLCCONF0_SLC0_TOKEN_AUTO_CLR Please initialize to 0. Do not modify it. (R/W)

SLCCONF0_SLC0_RX_AUTO_WRBACK Allows changing the owner bit of the transmitting buffer’s linked list when transmitting data. (R/W)

SLCCONF0_SLC0_RX_LOOP_TEST Loop around when the slave buffer finishes sending packets. When set to 1, hardware will not change the owner bit in the linked list. (R/W)

SLCCONF0_SLC0_TX_LOOP_TEST Loop around when the slave buffer finishes receiving packets. When set to 1, hardware will not change the owner bit in the linked list. (R/W)

SLCCONF0_SLC0_RX_RST Set this bit to reset the transmitting FSM. (R/W)

SLCCONF0_SLC0_TX_RST Set this bit to reset the receiving FSM. (R/W)

Espressif Systems

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ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

RAW

RAW_RAW

RAW RAW RAW RAW RAW RAW RAW RAW

_INT

RAW

_RAW

RAW

_RAW_RAW

ERR

_INT

INT

EOF

INT

_INT

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

EOF

OVF

BIT7 BIT6

DSCRDSCR

DONESUC

DONE

UDF

STARTSTART

_RX

_TX

_RX

_TX

_RX

_TX

_RX

FRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOST

SLC0 SLC0

SLC0

SLC0 SLC0 SLC0

SLC0 SLC0

SLC0 SLC0 SLC

SLC

(reserved)

SLC0INTSLC0INT(reserved)SLC0INTSLC0INTSLC0INTSLC0INT

(reserved)SLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INT

Reset

0x00

SLC0INT_SLC0_RX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave sending descriptor error (RO)

SLC0INT_SLC0_TX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave receiving descriptor error. (RO)

SLC0INT_SLC0_RX_EOF_INT_RAW The interrupt mark bit for Slave sending operation finished. (RO)

SLC0INT_SLC0_RX_DONE_INT_RAW The raw interrupt bit to mark single buffer as sent by Slave. (RO)

SLC0INT_SLC0_TX_SUC_EOF_INT_RAW The raw interrupt bit to mark Slave receiving operation as finished. (RO)

SLC0INT_SLC0_TX_DONE_INT_RAW The raw interrupt bit to mark a single buffer as finished during Slave receiving operation. (RO)

SLC0INT_SLC0_TX_OVF_INT_RAW The raw interrupt bit to mark Slave receiving buffer overflow. (RO)

SLC0INT_SLC0_RX_UDF_INT_RAW The raw interrupt bit for Slave sending buffer underflow. (RO)

SLC0INT_SLC0_TX_START_INT_RAW The raw interrupt bit for registering Slave receiving initialization interrupt. (RO)

SLC0INT_SLC0_RX_START_INT_RAW The raw interrupt bit to mark Slave sending initialization interrupt. (RO)

SLC0INT_SLC_FRHOST_BIT7_INT_RAW SLC0INT_SLC_FRHOST_BIT6_INT_RAW SLC0INT_SLC_FRHOST_BIT5_INT_RAW SLC0INT_SLC_FRHOST_BIT4_INT_RAW SLC0INT_SLC_FRHOST_BIT3_INT_RAW SLC0INT_SLC_FRHOST_BIT2_INT_RAW SLC0INT_SLC_FRHOST_BIT1_INT_RAW

SLC0INT_SLC_FRHOST_BIT0_INT_RAW

Espressif Systems

The interrupt mark bit 7 for Host to interrupt Slave. (RO)

The interrupt mark bit 6 for Host to interrupt Slave. (RO)

The interrupt mark bit 5 for Host to interrupt Slave. (RO)

The interrupt mark bit 4 for Host to interrupt Slave. (RO)

The interrupt mark bit 3 for Host to interrupt Slave. (RO)

The interrupt mark bit 2 for Host to interrupt Slave. (RO)

The interrupt mark bit 1 for Host to interrupt Slave. (RO)

The interrupt mark bit 0 for Host to interrupt Slave. (RO)

169 ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

INT

INT INT

INT

INT INT INT INT

ERR ERR

INT

EOF

INT

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

DSCRDSCR

EOF

DONESUC

DONE

OVF

UDF

STARTSTART

FRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOST

SLC0SLC0

SLC0SLC0SLC0SLC0

SLC0SLC0SLC0SLC0SLC

SLC SLC SLC

SLC SLC

SLC

(reserved)

SLC0INTSLC0INT(reserved)SLC0INTSLC0INTSLC0INTSLC0INT(reserved)SLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INT

Reset

0x00

SLC0INT_SLC0_RX_DSCR_ERR_INT_ST The interrupt status bit for Slave sending descriptor error. (RO)

SLC0INT_SLC0_TX_DSCR_ERR_INT_ST The interrupt status bit for Slave receiving descriptor error. (RO)

SLC0INT_SLC0_RX_EOF_INT_ST The interrupt status bit for finished Slave sending operation. (RO)

SLC0INT_SLC0_RX_DONE_INT_ST The interrupt status bit for finished Slave sending operation. (RO)

SLC0INT_SLC0_TX_SUC_EOF_INT_ST The interrupt status bit for marking Slave receiving operation as finished. (RO)

SLC0INT_SLC0_TX_DONE_INT_ST The interrupt status bit for marking a single buffer as finished during the receiving operation. (RO)

SLC0INT_SLC0_TX_OVF_INT_ST The interrupt status bit for Slave receiving overflow interrupt. (RO)

SLC0INT_SLC0_RX_UDF_INT_ST The interrupt status bit for Slave sending buffer underflow. (RO)

SLC0INT_SLC0_TX_START_INT_ST The interrupt status bit for Slave receiving interrupt initialization. (RO)

SLC0INT_SLC0_RX_START_INT_ST The interrupt status bit for Slave sending interrupt initialization. (RO)

SLC0INT_SLC_FRHOST_BIT7_INT_ST The interrupt status bit 7 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT6_INT_ST The interrupt status bit 6 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT5_INT_ST The interrupt status bit 5 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT4_INT_ST The interrupt status bit 4 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT3_INT_ST The interrupt status bit 3 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT2_INT_ST The interrupt status bit 2 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT1_INT_ST The interrupt status bit 1 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT0_INT_ST The interrupt status bit 0 for Host to interrupt Slave. (RO)

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ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

_ INT

ENA

_ ENA

ENA ENA ENA ENA ENA

ENA

ENA ENA

INT

ENA

_ INT

ENA

INT

ERR

INT

EOF

INT

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

DSCR

EOF

OVF

DONE

SUC

DONE

UDF

START START

SLC0

_ RX

_ TX

_ SLC0

SLC0

_ TX

_ RX

FRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOST

SLC0

_ SLC0

SLC

_ SLC

SLC

(reserved)

SLC0INTSLC0INT(reserved)SLC0INTSLC0INTSLC0INTSLC0INT

(reserved)

SLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INT

Reset

0x00

SLC0INT_SLC0_RX_DSCR_ERR_INT_ENA The interrupt enable bit for Slave sending linked list descriptor error. (R/W)

SLC0INT_SLC0_TX_DSCR_ERR_INT_ENA The interrupt enable bit for Slave receiving linked list descriptor error. (R/W)

SLC0INT_SLC0_RX_EOF_INT_ENA The interrupt enable bit for Slave sending operation completion. (R/W)

SLC0INT_SLC0_RX_DONE_INT_ENA The interrupt enable bit for single buffer’s sent interrupt, in Slave sending mode. (R/W)

SLC0INT_SLC0_TX_SUC_EOF_INT_ENA The interrupt enable bit for Slave receiving operation completion. (R/W)

SLC0INT_SLC0_TX_DONE_INT_ENA The interrupt enable bit for single buffer’s full event, in Slave receiving mode. (R/W)

SLC0INT_SLC0_TX_OVF_INT_ENA The interrupt enable bit for Slave receiving buffer overflow. (R/W)

SLC0INT_SLC0_RX_UDF_INT_ENA The interrupt enable bit for Slave sending buffer underflow. (R/W)

SLC0INT_SLC0_TX_START_INT_ENA The interrupt enable bit for Slave receiving operation initialization. (R/W)

SLC0INT_SLC0_RX_START_INT_ENA The interrupt enable bit for Slave sending operation initialization. (R/W)

SLC0INT_SLC_FRHOST_BIT7_INT_ENA SLC0INT_SLC_FRHOST_BIT6_INT_ENA SLC0INT_SLC_FRHOST_BIT5_INT_ENA SLC0INT_SLC_FRHOST_BIT4_INT_ENA SLC0INT_SLC_FRHOST_BIT3_INT_ENA SLC0INT_SLC_FRHOST_BIT2_INT_ENA SLC0INT_SLC_FRHOST_BIT1_INT_ENA

EspressifSLC0INTSystems_SLC_FRHOST_BIT0_INT_ENA

The interrupt enable bit 7 for Host to interrupt Slave. (R/W)

The interrupt enable bit 6 for Host to interrupt Slave. (R/W)

The interrupt enable bit 5 for Host to interrupt Slave. (R/W)

The interrupt enable bit 4 for Host to interrupt Slave. (R/W)

The interrupt enable bit 3 for Host to interrupt Slave. (R/W)

The interrupt enable bit 2 for Host to interrupt Slave. (R/W)

The interrupt enable bit 1 for Host to interrupt Slave. (R/W)

The interrupt171 enable bit 0 for Host to interruptESP32 SlaveTRM .(Version(R/W) 5.0)

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8 SDIO Slave Controller

_ INT

CLR

_ CLR

CLR CLR CLR CLR CLR

CLR

CLR CLR

INT

CLR

_ INT

CLR

INT

ERR

INT

EOF

INT

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

DSCR

EOF

OVF

DONE

SUC

DONE

UDF

START START

SLC0

_ RX

_ TX

_ SLC0

SLC0

_ TX

_ RX

FRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOSTFRHOST

SLC0

_ SLC0

SLC

_ SLC

SLC

(reserved)

SLC0INTSLC0INT(reserved)SLC0INTSLC0INTSLC0INTSLC0INT

(reserved)

SLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INTSLC0INT

Reset

0x00

SLC0INT_SLC0_RX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave sending linked list descriptor error. (WO)

SLC0INT_SLC0_TX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave receiving linked list descriptor error. (WO)

SLC0INT_SLC0_RX_EOF_INT_CLR Interrupt clear bit for Slave sending operation completion. (WO)

SLC0INT_SLC0_RX_DONE_INT_CLR Interrupt clear bit for single buffer’s sent interrupt, in Slave sending mode. (WO)

SLC0INT_SLC0_TX_SUC_EOF_INT_CLR Interrupt clear bit for Slave receiving operation completion. (WO)

SLC0INT_SLC0_TX_DONE_INT_CLR Interrupt clear bit for single buffer’s full event, in Slave receiving mode. (WO)

SLC0INT_SLC0_TX_OVF_INT_CLR Set this bit to clear the Slave receiving overflow interrupt. (WO)

SLC0INT_SLC0_RX_UDF_INT_CLR Set this bit to clear the Slave sending underflow interrupt. (WO)

SLC0INT_SLC0_TX_START_INT_CLR Set this bit to clear the interrupt for Slave receiving operation initialization. (WO)

SLC0INT_SLC0_RX_START_INT_CLR Set this bit to clear the interrupt for Slave sending operation initialization. (WO)

SLC0INT_SLC_FRHOST_BIT7_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT7_INT interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT6_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT6_INT interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT5_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT5_INT interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT4_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT4_INT interrupt. (WO)

Continued on the next page...

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ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

Continued from the previous page...

SLC0INT_SLC_FRHOST_BIT3_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT3_INT interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT2_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT2_INT interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT1_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT1_INT interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT0_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT0_INT interrupt. (WO)

											Register 8.6. SLC0RX_LINK_REG (0x3C)
						RESTARTSTARTSTOP							ADDR
						_	_	_					_
					RXLINKRXLINKRXLINK								RXLINK
				_		_	_						_
			SLC0SLC0SLC0										SLC0
		_		_		_			(reserved)				_
(reserved)SLC0RXSLC0RXSLC0RX									(reserved)				SLC0RX
31	30	29	28		27							20	19	0
															Reset

0	0	0	0		0	0	0	0	0	0	0	0	0x000000

SLC0RX_SLC0_RXLINK_RESTART Set this bit to restart and continue the linked list operation for sending packets. (R/W)

SLC0RX_SLC0_RXLINK_START Set this bit to start the linked list operation for sending packets. Sending will start from the address indicated by SLC0_RXLINK_ADDR. (R/W)

SLC0RX_SLC0_RXLINK_STOP Set this bit to stop the linked list operation. (R/W)

SLC0RX_SLC0_RXLINK_ADDR The lowest 20 bits in the initial address of Slave’s sending linked list. (R/W)

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8 SDIO Slave Controller

										Register 8.7. SLC0TX_LINK_REG (0x40)
					RESTARTSTARTSTOP							ADDR
					_	_	_					_
				TXLINKTXLINKTXLINK								TXLINK
			_		_	_						_
			SLC0SLC0SLC0					(reserved)				SLC0
(reserved)SLC0TXSLC0TXSLC0TX								(reserved)				SLC0TX
		_	_		_							_

31	30	29	28	27							20	19	0
														Reset

0	0	0	0	0	0	0	0	0	0	0	0	0x000000

SLC0TX_SLC0_TXLINK_RESTART Set this bit to restart and continue the linked list operation for receiving packets. (R/W)

SLC0TX_SLC0_TXLINK_START Set this bit to start the linked list operation for receiving packets. Receiving will start from the address indicated by SLC0_TXLINK_ADDR. (R/W)

SLC0TX_SLC0_TXLINK_STOP Set this bit to stop the linked list operation for receiving packets. (R/W)

SLC0TX_SLC0_TXLINK_ADDR The lowest 20 bits in the initial address of Slave’s receiving linked list. (R/W)

															INTVEC
														_
														TOHOST
														_
														SLC0
														_
(reserved)						(reserved)					(reserved)		SLCINTVEC
31	24	23							16	15	8	7		0
															Reset

0x000		0	0	0	0	0	0	0	0		0x000		0x000

SLCINTVEC_SLC0_TOHOST_INTVEC The interrupt vector for Slave to interrupt Host. (WO)

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ESP32 TRM (Version 5.0)

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8 SDIO Slave Controller

WDATA

INC

TOKEN1

SLC0

(reserved)

SLC0TOKEN1

(reserved)SLC0TOKEN1(reserved)

SLC0TOKEN1

Reset

0x00

0x0000

SLC0TOKEN1_SLC0_TOKEN1 The accumulated number of buffers for receiving packets. (RO)

SLC0TOKEN1_SLC0_TOKEN1_INC_MORE Set this bit to add the value of SLC0TOKEN1_SLC0_TOKEN1_WDATA to that of SLC0TOKEN1_SLC0_TOKEN1. (WO)

SLC0TOKEN1_SLC0_TOKEN1_WDATA The number of available receiving buffers. (WO)

																								EN	EN	CLR
																								_	_	_
																						STITCHSTITCH
																					_		_	LEN	AUTO
																					RX		TX	LEN
																					_	_		_
																				SLC0SLC0SLC0
																				_	_	_
(reserved)					(reserved)								(reserved)					SLCCONF1SLCCONF1SLCCONF1
31	23	22						16	15								7	6	5	4
																					Reset

0x000		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1

SLCCONF1_SLC0_RX_STITCH_EN SLCCONF1_SLC0_TX_STITCH_EN SLCCONF1_SLC0_LEN_AUTO_CLR

Please initialize to 0. Do not modify it. (R/W)

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175

ESP32 TRM (Version 5.0)

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