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5 DPort Registers

5.5Registers

The addresses in parenthesis besides register names are the register addresses relative to the DPORT base address provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 5.4 Register Summary.

																																REMAP
																																_
																																BOOT
																																_
															(reserved)																	PRO
															(reserved)																DPORT
																																_

31																														1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

DPORT_PRO_BOOT_REMAP Remap mode for PRO_CPU. (R/W)

																																REMAP
																																_
																																BOOT
																																_
															(reserved)																	APP
															(reserved)																DPORT
																																_

31																														1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

DPORT_APP_BOOT_REMAP Remap mode for APP_CPU. (R/W)

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																																		RSA		SHA AES
																																	_		_		_
																																	EN		EN		EN
																																_		_		_
															(reserved)																PERI PERI PERI
															(reserved)															DPORTDPORTDPORT
																															_	_		_

31																													3	2	1	0
																																	Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

DPORT_PERI_EN_RSA Set the bit to enable the clock of RSA module. Clear the bit to disable the clock of RSA module. (R/W)

DPORT_PERI_EN_SHA Set the bit to enable the clock of SHA module. Clear the bit to disable the clock of SHA module. (R/W)

DPORT_PERI_EN_AES Set the bit to enable the clock of AES module. Clear the bit to disable the clock of AES module. (R/W)

																																	RSA		SHA AES
																																	_	_		_
																																	RST RST		RST
																																_	_	_
															(reserved)																PERI PERI PERI
															(reserved)															DPORTDPORTDPORT
																															_	_	_

31																													3	2	1	0
																																	Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

DPORT_PERI_RST_RSA Set the bit to reset RSA module. (R/W)

DPORT_PERI_RST_SHA Set the bit to reset SHA module. (R/W)

Clear the bit to release RSA module.

Clear the bit to release SHA module.

DPORT_PERI_RST_AES Set the bit to reset AES module. Clear the bit to release AES module. (R/W)

																																RESETTING
																																_
															(reserved)																	APPCPU
															(reserved)																DPORT
																																_

31																														1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1

DPORT_APPCPU_RESETTING Set to 1 to reset APP_CPU. Clear the bit to release APP_CPU. (R/W)

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																																	EN
																																_
																																CLKGATE
																																_
															(reserved)																	APPCPU
															(reserved)																DPORT
																																_

31																														1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

DPORT_APPCPU_CLKGATE_EN Set to 1 to enable the clock of APP_CPU. Clear the bit to disable the clock of APP_CPU. (R/W)

																																RUNSTALL
																																_
															(reserved)																	APPCPU
															(reserved)																DPORT
																																_

31																														1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

DPORT_APPCPU_RUNSTALL Set to 1 to put APP_CPU into stalled state. Clear the bit to release APP_CPU from stalled state. (R/W)

31	0
		Reset

0x000000000

DPORT_APPCPU_CTRL_REG_D_REG When APP_CPU is booted up with ROM code, it will jump to the address stored in this register. (R/W)

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																																SEL
																																_
																																CPUPERIOD
																																_
															(reserved)																	CPU
															(reserved)																DPORT
																																_

31																													2	1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

DPORT_CPU_CPUPERIOD_SEL Select CPU clock. Refer to Table 3-3 for details. (R/W)

																														ENA							DONEENA
																												IRAM							FLUSHFLUSHENABLE
																					HL						SPLIT		_
																					HL						SPLIT								_	_	_
																			DRAM								_						CACHECACHECACHE
																			DRAM					DRAMSINGLE									CACHECACHECACHE
																				_
																		_						_		_							_	_	_
							(reserved)								DPORT		PRO		(reserved)				PRO PRO				(reserved)					PRO PRO PRO
							(reserved)								DPORT				(reserved)			DPORTDPORT					(reserved)		DPORTDPORTDPORT						(reserved)
																_							_	_								_	_	_

31														17	16	15					12	11	10	9				6	5		4		3	2		0
																																					Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0		0	0	0	0	0		0	0	0		1		0	0	0	0

DPORT_PRO_DRAM_HL Determines the virtual address mode of the external SRAM. (R/W)

DPORT_PRO_DRAM_SPLIT Determines the virtual address mode of the external SRAM. (R/W)

DPORT_PRO_SINGLE_IRAM_ENA Determines a special mode for PRO_CPU access to the external flash. (R/W)

DPORT_PRO_CACHE_FLUSH_DONE PRO_CPU cache-flush done. (RO)

DPORT_PRO_CACHE_FLUSH_ENA Flushes the PRO_CPU cache. (R/W)

DPORT_PRO_CACHE_ENABLE Enables the PRO_CPU cache. (R/W)

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																										_								OPSDRAMDROM0DRAM1IROM0IRAM1IRAM0
																									IA		CLR							_	_		_	_	_	_
																								_									MASKMASKMASKMASKMASKMASK
																						MMU											MASKMASKMASKMASKMASKMASK
																						_		PD									_	_	_	_		_	_
																							_								CACHECACHECACHECACHECACHECACHE
																				CACHECMMU											CACHECACHECACHECACHECACHECACHE
																				_	_										_	_	_	_	_		_
									(reserved)										PRO PRO				(reserved)							PRO PRO PRO PRO PRO						PRO
																			_	_										_	_	_	_	_	_
																		DPORTDPORT											DPORTDPORTDPORTDPORTDPORTDPORT
31																	14	13	12	11								6	5	4	3	2	1	0
																																			Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0			0	0	1	1	1	1	1	1

DPORT_PRO_CACHE_MMU_IA_CLR Clears PRO cache MMU error flag. (R/W)

DPORT_PRO_CMMU_PD Disables PRO cache MMU. (R/W)

DPORT_PRO_CACHE_MASK_OPSDRAM Disables access from APP_CPU DRAM1 to PRO cache. 1: Disable

0: Enable (R/W)

DPORT_PRO_CACHE_MASK_DROM0 Disables access from PRO_CPU DROM0 to PRO cache. 1: Disable

0: Enable (R/W)

DPORT_PRO_CACHE_MASK_DRAM1 Disables access from PRO_CPU DRAM1 to PRO cache. 1: Disable

0: Enable (R/W)

DPORT_PRO_CACHE_MASK_IROM0 Disables access from PRO_CPU IROM0 to PRO cache. 1: Disable

0: Enable (R/W)

DPORT_PRO_CACHE_MASK_IRAM1 Disables access from PRO_CPU IRAM1 to PRO cache. 1: Disable

0: Enable (R/W)

DPORT_PRO_CACHE_MASK_IRAM0 Disables access from PRO_CPU IRAM0 to PRO cache. 1: Disable

0: Enable (R/W)

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																															ENA						DONEENA
																													IRAM							FLUSHFLUSHENABLE
																						HL						SPLIT		_
																						HL						SPLIT								_	_	_
																			DRAM									_						CACHECACHECACHE
																			DRAM							DRAMSINGLE								CACHECACHECACHE
																					_
																			_						_		_							_	_	_
								(reserved)											APP				APP			APP		(reserved)					APP APP APP
								(reserved)									DPORT (reserved)DPORTDPORT											(reserved)		DPORTDPORTDPORT						(reserved)
																			_			_			_								_	_	_

31																15	14	13	12	11		10		9					6	5		4		3	2		0
																																						Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0		0		0		0	0	0		1		0	0	0	0

DPORT_APP_DRAM_HL Determines the virtual address mode of the External SRAM. (R/W)

DPORT_APP_DRAM_SPLIT Determines the virtual address mode of the External SRAM. (R/W)

DPORT_APP_SINGLE_IRAM_ENA Determines a special mode for APP_CPU access to the external flash. (R/W)

DPORT_APP_CACHE_FLUSH_DONE APP_CPU cache-flush done. (RO)

DPORT_APP_CACHE_FLUSH_ENA Flushes the APP_CPU cache. (R/W)

DPORT_APP_CACHE_ENABLE Enables the APP_CPU cache. (R/W)

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																										_								OPSDRAMDROM0DRAM1IROM0IRAM1IRAM0
																									IA		CLR							_	_		_	_	_	_
																								_									MASKMASKMASKMASKMASKMASK
																						MMU											MASKMASKMASKMASKMASKMASK
																						_		PD									_	_	_	_		_	_
																							_								CACHECACHECACHECACHECACHECACHE
																					CACHECMMU										CACHECACHECACHECACHECACHECACHE
																				_	_										_	_	_	_	_		_
									(reserved)										APP		APP		(reserved)							APP APP APP APP APP						APP
																			_	_										_	_	_	_	_	_
																		DPORTDPORT											DPORTDPORTDPORTDPORTDPORTDPORT
31																	14	13	12	11								6	5	4	3	2	1	0
																																			Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0			0	0	1	1	1	1	1	1

DPORT_APP_CACHE_MMU_IA_CLR Clears APP cache MMU error flag. (R/W)

DPORT_APP_CMMU_PD Disables APP cache MMU. (R/W)

DPORT_APP_CACHE_MASK_OPSDRAM Disables access from PRO_CPU DRAM1 to APP cache. 1: Disable

0: Enable (R/W)

DPORT_APP_CACHE_MASK_DROM0 Disables access from APP_CPU DROM0 to APP cache. 1: Disable

0: Enable (R/W)

DPORT_APP_CACHE_MASK_DRAM1 Disables access from APP_CPU DRAM1 to APP cache. 1: Disable

0: Enable (R/W)

DPORT_APP_CACHE_MASK_IROM0 Disables access from APP_CPU IROM0 to APP cache. 1: Disable

0: Enable (R/W)

DPORT_APP_CACHE_MASK_IRAM1 Disables access from APP_CPU IRAM1 to APP cache. 1: Disable

0: Enable (R/W)

DPORT_APP_CACHE_MASK_IRAM0 Disables access from APP_CPU IRAM0 to APP cache. 1: Disable

0: Enable (R/W)

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																																MODE
																																_
																																MUX
																																_
															(reserved)																	CACHE
															(reserved)																DPORT
																																_

31																													2	1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

DPORT_CACHE_MUX_MODE The mode of the two caches sharing the memory. (R/W)

																																MODE
																																_
																																PAGE
																																_
														(reserved)																	IMMU
														(reserved)																DPORT (reserved)
																															_

31																												3	2	1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

DPORT_IMMU_PAGE_MODE Page size in the MMU for the internal SRAM 0. (R/W)

																																MODE
																																_
																																PAGE
																																_
														(reserved)																	DMMU
														(reserved)																DPORT (reserved)
																															_

31																												3	2	1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

DPORT_DMMU_PAGE_MODE Page size in the MMU for the internal SRAM 2. (R/W)

31	0
		Reset

0xFFFFFFFF

DPORT_AHB_MPU_TABLE_0_REG MPU for DMA. (R/W)

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						1
				_
				GRANT
				_
				ACCESS
				_
(reserved)				AHB
(reserved)			DPORT
				_

31	9	8		0
					Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0	0 0 0 0 0 0 0		0x1FF

DPORT_AHB_ACCESS_GRANT_1 MPU for DMA. (R/W)

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CLK

CLK _

UARTUART2SPI

UHCI0I2C

UARTSPI01

I2S1 PWM1TWAI I2C

PWM0SPI3

TIMERGROUP1EFUSETIMERGROUPUHCI1LEDCPCNTRMT

SPI2 UART1I2S0

CLK

MEM

CLK

CLK _

CLK

CLK CLK

CLK

DMA

EXT1

EXT0

(reserved)

(reserved)(reserved)DPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORT(reserved)DPORTDPORT(reserved)

Reset

11111

Set the following bit to enable the clock of the corresponding module. Clear the bit to disable the clock of the corresponding module.

DPORT_UART_MEM_CLK_EN Shared memory of UART0 ~ 2. To use any UART peripherals, enable the clock for UART memory. (R/W)

DPORT_UART2_CLK_EN UART2 module. (R/W)

DPORT_SPI_DMA_CLK_EN SPI_DMA module. (R/W)

DPORT_I2S1_CLK_EN I2S1 module. (R/W)

DPORT_PWM1_CLK_EN PWM1 module. (R/W)

DPORT_TWAI_CLK_EN TWAI module. (R/W)

DPORT_I2C_EXT1_CLK_EN I2C1 module. (R/W)

DPORT_PWM0_CLK_EN PWM0 module. (R/W)

DPORT_SPI3_CLK_EN SPI3 module. (R/W)

DPORT_TIMERGROUP1_CLK_EN TIMG1 module. (R/W)

DPORT_EFUSE_CLK_EN eFuse module. (R/W)

DPORT_TIMERGROUP_CLK_EN TIMG0 module. (R/W)

DPORT_UHCI1_CLK_EN UDMA1 module. (R/W)

DPORT_LEDC_CLK_EN LEDC module. (R/W)

DPORT_PCNT_CLK_EN PCNT module. (R/W)

DPORT_RMT_CLK_EN RMT module. (R/W)

DPORT_UHCI0_CLK_EN UDMA0 module. (R/W)

DPORT_I2C_EXT0_CLK_EN I2C0 module. (R/W)

DPORT_SPI2_CLK_EN SPI2 module. (R/W)

Continued on the next page...

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Continued from the previous page...

DPORT_UART1_CLK_EN UART1 module. (R/W)

DPORT_I2S0_CLK_EN I2S0 module. (R/W)

DPORT_UART_CLK_EN UART0 module. (R/W)

DPORT_SPI01_CLK_EN SPI0 and SPI1 module. (R/W)

RST

SPI2

UART1I2S0

UARTSPI01

UARTUART2SPI

I2S1

PWM1TWAI I2C PWM0SPI3 TIMERGROUP1TIMERGROUPEFUSE UHCI1LEDCPCNTRMT UHCI0I2C

RST

MEM

RST

RST RST

RST

EXT1

EXT0

DMA _

(reserved)

(reserved)(reserved)DPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORTDPORT(reserved)DPORTDPORT(reserved)

Reset

00000

Set each bit to reset the corresponding module. Clear the bit to release the corresponding module. For the list of modules, please refer to register 5.19.

																									EN										EN
																								_										_
																						_	HOST										SDIOSLAVE
																					EMACSDIO												SDIOSLAVE
																						EN	_
																							_
																				_	_											_
																				CLK	CLK											CLK
																			_	_											_
								(reserved)										WIFI		WIFI			(reserved)					DPORT		WIFI		(reserved)
								(reserved)									DPORTDPORT						(reserved)					DPORT				(reserved)
																		_	_										_

31																15	14	13	12								5	4	3				0
																																		Reset

1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	1	1	1	0	0	0	0	0		0	0	1	1	0	0		0	0

DPORT_WIFI_CLK_EMAC_EN Set the bit to enable the clock of Ethernet MAC module. Clear the bit to disable the clock of Ethernet MAC module. (R/W)

DPORT_WIFI_CLK_SDIO_HOST_EN Set the bit to enable the clock of SD/MMC module. Clear the bit to disable the clock of SD/MMC module. (R/W)

DPORT_WIFI_CLK_SDIOSLAVE_EN Set the bit to enable the clock of SDIO module. Clear the bit to disable the clock of SDIO module. (R/W)

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																															RST
																															_
																											_		HOSTRST
																											RST			_
																												_		_
												(reserved)													EMACSDIO SDIO						(reserved)
												(reserved)												DPORTDPORTDPORT							(reserved)
																									_	_		_

31																							8	7	6	5	4						0
																																		Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0		0	0	0

DPORT_EMAC_RST Set the bit to reset Ethernet MAC module. Clear the bit to release Ethernet MAC module. (R/W)

DPORT_SDIO_HOST_RST Set the bit to reset SD/MMC module. Clear the bit to release SD/MMC module. (R/W)

DPORT_SDIO_RST Set the bit to reset SDIO module. Clear the bit to release SDIO module. (R/W)

																																n
																																_
																																CPU
																																_
																																FROM
																																_
																																INTR
																																_
															(reserved)																	CPU
																																_
																															DPORT
31																														1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
	DPORT_CPU_INTR_FROM_CPU_n												Interrupt in both CPUs. (R/W)
				Register 5.24. DPORT_PRO_INTR_STATUS_REG_n_REG (n: 02) (0xEC+4*n)

31																															0
																																Reset

														0x000000000
	DPORT_PRO_INTR_STATUS_REG_n_REG														PRO_CPU interrupt status. (RO)
				Register 5.25. DPORT_APP_INTR_STATUS_REG_n_REG (n: 02) (0xF8+4*n)

31																															0
																																Reset

														0x000000000
	DPORT_APP_INTR_STATUS_REG_n_REG														APP_CPU interrupt status. (RO)

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																															MAP
																														_
																													*
																													_
													(reserved)																PRO
													(reserved)															DPORT
																													_

31																										5	4		0
																														Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		10000

DPORT_PRO_*_MAP Interrupt map. (R/W)

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																															MAP
																														_
																													*
																													_
													(reserved)																APP
													(reserved)															DPORT
																													_

31																										5	4		0
																														Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		10000

DPORT_APP_*_MAP Interrupt map. (R/W)

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5 DPort Registers

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ESP32 TRM (Version 5.0)

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5 DPort Registers

																																			CONFIG
																																			_
																																			GRANT
																																			_
																																			ACCESS
																																		_
																																*
																																_
													(reserved)																	AHBLITE
													(reserved)																DPORT
																														_

31																									6	5					0
																																	Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
	DPORT_AHBLITE_*_ACCESS_GRANT_CONFIG																MPU for peripherals. (R/W)

																												n
																											TABLE
																											_
												(reserved)															IMMU
												(reserved)														DPORT
																											_

31																								7	6		0
																												Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0000000

DPORT_IMMU_TABLEn MMU for internal SRAM. When n is 0 ~ 9, the reset value is 0. When n is 10

~ 15, the reset value is 10, 11, 12, 13, 14, 15, respectively. (R/W)

																												n
																											TABLE
																											_
												(reserved)															DMMU
												(reserved)														DPORT
																											_

31																								7	6		0
																												Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0000000

DPORT_DMMU_TABLEn MMU for internal SRAM. When n is 0 ~ 15, the reset value is 0 ~ 15, respectively. (R/W)

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ESP32 TRM (Version 5.0)

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5 DPort Registers

																																			SEL		SEL	SEL
																																		_		_		_
																																CHAN			CHAN		CHAN
																																_			_		_
																															DMA			DMA		DMA
																													_				_			_
																													SPI3			SPI2			SPI1
																													_			_			_
													(reserved)															SPI			SPI			SPI
													(reserved)														DPORT		DPORT			DPORT
																												_		_				_

31																									6	5	4	3	2		1		0
																																		Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0		0

DPORT_SPI_SPI3_DMA_CHAN_SEL Selects DMA channel for SPI3. (R/W)

DPORT_SPI_SPI2_DMA_CHAN_SEL Selects DMA channel for SPI2. (R/W)

DPORT_SPI_SPI1_DMA_CHAN_SEL Selects DMA channel for SPI1. (R/W)

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ESP32 TRM (Version 5.0)

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