5DPort Registers

5DPort Registers

5.1Introduction

The ESP32 integrates a large number of peripherals, and enables the control of individual peripherals to achieve optimal characteristics in performance-vs-power-consumption scenarios. The DPort registers control clock management (clock gating), power management, and the configuration of peripherals and core-system modules. The system arranges each module with configuration registers contained in the DPort Register.

5.2Features

DPort registers correspond to different peripheral blocks and core modules:

•System and memory

•Reset and clock

•Interrupt matrix

•DMA

•MPU/MMU

•APP_CPU controller

•Peripheral clock gating and reset

5.3Functional Description

5.3.1System and Memory Register

System and memory registers are used for system and memory configuration, such as cache configuration and memory remapping. They are listed in Section 5.4, categorized as ”System and memory registers”. For a detailed description of these registers, please refer to Chapter System and Memory.

5.3.2Reset and Clock Registers

Reset and clock registers are listed in Section 5.4, categorized as ”Reset and clock registers”. For a detailed description of these registers, please refer to Chapter Reset and Clock.

5.3.3Interrupt Matrix Register

The interrupt matrix registers are used for configuring and mapping interrupts through the interrupt matrix. They are listed in Section 5.4, categorized as ”Interrupt matrix registers”. For a detailed description of these registers, please refer to Chapter Interrupt Matrix (INTERRUPT).

5.3.4DMA Registers

DMA registers are used for the SPI DMA configuration. They are listed in Section 5.4, categorized as ”DMA registers”. For a detailed description of these registers, please refer to Chapter DMA Controller (DMA).

5.3.5MPU/MMU Registers

MPU/MMU registers are used for MPU/MMU configuration and operation control. They are listed in Section 5.4, categorized as ”MPU/MMU registers”. For a detailed description of these registers, please refer to Chapter Memory Management and Protection Units (MMU, MPU).

Submit Documentation Feedback

5 DPort Registers

5.3.6APP_CPU Controller Registers

APP_CPU controller registers are used for some basic configuration of the APP_CPU, such as performing a stalling execution, and for configuring the ROM boot jump address. The registers are listed in Section 5.4, categorized as ”APP_CPU controller registers”. A detailed description of these registers is provided in section 5.5. Note that reset bits are not self-clearing.

5.3.7Peripheral Clock Gating and Reset

The following registers are used for controlling the clock gating and reset of different peripherals. A detailed description of these registers is provided in section 5.5.

•DPORT_PERI_CLK_EN_REG

•DPORT_PERI_RST_EN_REG

•DPORT_PERIP_CLK_EN_REG

•DPORT_PERIP_RST_EN_REG

•DPORT_WIFI_CLK_EN_REG

•DPORT_WIFI_RST_EN_REG

Notice:

•Clock gating and reset registers are active high.

•Reset registers cannot be cleared by hardware. Therefore, SW reset clear is required after setting the reset registers.

•ESP32 features low power consumption. This is why some peripheral clocks are gated (disabled) by default. Before using any of these peripherals, it is mandatory to enable the clock for the given peripheral by setting the corresponding CLK_EN bit to 1, and release the peripheral from reset state to make it operational by setting the RST_EN bit to 0.

Submit Documentation Feedback