4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

4.13Registers

4.13.1 GPIO Matrix Registers

The addresses in parenthesis besides register names are the register addresses relative to the GPIO base address provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 4.12.1 GPIO Matrix Register Summary.

Register 4.1. GPIO_OUT_REG (0x0004)

GPIO_OUT_REG GPIO0-31 output value. (R/W)

Register 4.2. GPIO_OUT_W1TS_REG (0x0008)

GPIO_OUT_W1TS_REG GPIO0-31 output set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_OUT_REG will be set. (WO)

Register 4.3. GPIO_OUT_W1TC_REG (0x000c)

GPIO_OUT_W1TC_REG GPIO0-31 output clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_OUT_REG will be cleared. (WO)

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Register 4.4. GPIO_OUT1_REG (0x0010)

GPIO_OUT_DATA GPIO32-39 output value. (R/W)

Register 4.5. GPIO_OUT1_W1TS_REG (0x0014)

GPIO_OUT_DATA GPIO32-39 output value set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_OUT1_DATA will be set. (WO)

Register 4.6. GPIO_OUT1_W1TC_REG (0x0018)

GPIO_OUT_DATA GPIO32-39 output value clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_OUT1_DATA will be cleared. (WO)

Register 4.7. GPIO_ENABLE_REG (0x0020)

GPIO_ENABLE_REG GPIO0-31 output enable. (R/W)

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Register 4.8. GPIO_ENABLE_W1TS_REG (0x0024)

GPIO_ENABLE_W1TS_REG GPIO0-31 output enable set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_ENABLE will be set. (WO)

Register 4.9. GPIO_ENABLE_W1TC_REG (0x0028)

GPIO_ENABLE_W1TC_REG GPIO0-31 output enable clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_ENABLE will be cleared. (WO)

Register 4.10. GPIO_ENABLE1_REG (0x002c)

GPIO_ENABLE_DATA GPIO32-39 output enable. (R/W)

Register 4.11. GPIO_ENABLE1_W1TS_REG (0x0030)

GPIO_ENABLE_DATA GPIO32-39 output enable set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_ENABLE1 will be set. (WO)

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Register 4.12. GPIO_ENABLE1_W1TC_REG (0x0034)

GPIO_ENABLE_DATA GPIO32-39 output enable clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_ENABLE1 will be cleared. (WO)

Register 4.13. GPIO_STRAP_REG (0x0038)

GPIO_STRAPPING GPIO strapping results: Bit5-bit0 of boot_sel_chip[5:0] correspond to MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5, respectively.

Register 4.14. GPIO_IN_REG (0x003c)

GPIO_IN_REG GPIO0-31 input value. Each bit represents a pad input value, 1 for high level and 0

for low level. (RO)

Register 4.15. GPIO_IN1_REG (0x0040)

GPIO_IN_DATA_NEXT GPIO32-39 input value. Each bit represents a pad input value. (RO)

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Register 4.16. GPIO_STATUS_REG (0x0044)

GPIO_STATUS_REG GPIO0-31 interrupt status register. Each bit can be either of the two interrupt sources for the two CPUs. The enable bits in GPIO_STATUS_INTERRUPT, corresponding to the 0-4 bits in GPIO_PINn_REG should be set to 1. (R/W)

Register 4.17. GPIO_STATUS_W1TS_REG (0x0048)

GPIO_STATUS_W1TS_REG GPIO0-31 interrupt status set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set. (WO)

Register 4.18. GPIO_STATUS_W1TC_REG (0x004c)

GPIO_STATUS_W1TC_REG GPIO0-31 interrupt status clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. (WO)

Register 4.19. GPIO_STATUS1_REG (0x0050)

GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status. (R/W)

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Register 4.20. GPIO_STATUS1_W1TS_REG (0x0054)

GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be set. (WO)

Register 4.21. GPIO_STATUS1_W1TC_REG (0x0058)

GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be cleared. (WO)

Register 4.22. GPIO_ACPU_INT_REG (0x0060)

GPIO_ACPU_INT_REG GPIO0-31 APP CPU interrupt status. (RO)

Register 4.23. GPIO_ACPU_NMI_INT_REG (0x0064)

GPIO_ACPU_NMI_INT_REG GPIO0-31 APP CPU non-maskable interrupt status. (RO)

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Register 4.24. GPIO_PCPU_INT_REG (0x0068)

GPIO_PCPU_INT_REG GPIO0-31 PRO CPU interrupt status. (RO)

Register 4.25. GPIO_PCPU_NMI_INT_REG (0x006c)

GPIO_PCPU_NMI_INT_REG GPIO0-31 PRO CPU non-maskable interrupt status. (RO)

Register 4.26. GPIO_ACPU_INT1_REG (0x0074)

GPIO_APPCPU_INT GPIO32-39 APP CPU interrupt status. (RO)

Register 4.27. GPIO_ACPU_NMI_INT1_REG (0x0078)

GPIO_APPCPU_NMI_INT GPIO32-39 APP CPU non-maskable interrupt status. (RO)

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Register 4.28. GPIO_PCPU_INT1_REG (0x007c)

GPIO_PROCPU_INT GPIO32-39 PRO CPU interrupt status. (RO)

Register 4.29. GPIO_PCPU_NMI_INT1_REG (0x0080)

GPIO_PROCPU_NMI_INT GPIO32-39 PRO CPU non-maskable interrupt status. (RO)

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Register 4.30. GPIO_PINn_REG (n: 0­39) (0x88+0x4*n)

GPIO_PINn_INT_ENA Interrupt enable bits for pin n: (R/W) bit0: APP CPU interrupt enable;

bit1: APP CPU non-maskable interrupt enable; bit2: PRO CPU interrupt enable;

bit3: PRO CPU non-maskable interrupt enable.

GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable will only wake up the CPU from Light-sleep. (R/W)

GPIO_PINn_INT_TYPE Interrupt type selection: (R/W)

0:GPIO interrupt disable;

1:rising edge trigger;

2:falling edge trigger;

3:any edge trigger;

4:low level trigger;

5:high level trigger.

GPIO_PINn_PAD_DRIVER 0: normal output; 1: open drain output. (R/W)

Register 4.31. GPIO_FUNCy_IN_SEL_CFG_REG (y: 0­255) (0x130+0x4*y)

GPIO_SIGy_IN_SEL Bypass the GPIO Matrix. 1: route through GPIO Matrix, 0: connect signal directly to peripheral configured in the IO_MUX. (R/W)

GPIO_FUNCy_IN_INV_SEL Invert the input value. 1: invert; 0: do not invert. (R/W)

GPIO_FUNCy_IN_SEL Selection control for peripheral input y. A value of 0-39 selects which of the 40 GPIO Matrix input pins this signal is connected to, or 0x38 for a constantly high input or 0x30 for a constantly low input. (R/W)

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