4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

4.6Light­sleep Mode Pin Functions

Pins can have different functions when the ESP32 is in Light-sleep mode. If the SLP_SEL bit in the IO_MUX register for a GPIO pad is set to 1, a different set of registers is used to control the pad when the ESP32 is in Light-sleep mode:

Table 4­1. IO_MUX Light­sleep Pin Function Registers

If SLP_SEL is set to 0, the pin functions remain the same in both normal execution and Light-sleep mode.

4.7Pad Hold Feature

Each IO pad (including the RTC pads) has an individual hold function controlled by a RTC register. When the pad is set to hold, the state is latched at that moment and will not change no matter how the internal signals change or how the IO_MUX configuration or GPIO configuration is modified. Users can use the hold function for the pads to retain the pad state through a core reset and system reset triggered by watchdog time-out or Deep-sleep events.

Note:

•For digital pads, to maintain the pad’s input/output status in Deep-sleep mode, you can set REG_DG_PAD_FORCE_UNHOLD to 0 before powering down.

For RTC pads, the input and output values are controlled by the corresponding bits of register RTC_CNTL_HOLD_FORCE_REG, and you can set it to 1 to hold the value or set it to 0 to unhold the value.

•For digital pads, to disable the hold function after the chip is woken up, you can set REG_DG_PAD_FORCE_UNHOLD to 1. To maintain the hold function of the pad, you can change the corresponding bit in the register by setting RTC_CNTL_HOLD_FORCE_REG to 1.

4.8I/O Pad Power Supplies

Figure 4-4 and 4-5 show the IO pad power supplies.

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Figure 4­4. ESP32 I/O Pad Power Sources (QFN 6*6, Top View)

Figure 4­5. ESP32 I/O Pad Power Sources (QFN 5*5, Top View)

• Pads marked blue are RTC pads that have their individual analog function and can also act as normal digital

Espressif Systems 54 ESP32 TRM (Version 5.0)

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