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31 Low-Power Management (RTC_CNTL)

entry address.

The boot flow is shown in Figure 31-11.

Figure 3111. ESP32 Boot Flow

31.4Register Summary

Notes:

•The registers listed below have been grouped according to their functionality. This particular grouping does not reflect the exact sequential order in which they are stored in memory.

•The base address for registers is 0x60008000 when accessed by AHB, and 0x3FF48000 when accessed by DPORT bus.

Name	Description		Address	Access
RTC option register

RTC_CNTL_OPTIONS0_REG	Configure RTC options		0x3FF48000	R/W

Control and configuration of RTC timer registers

RTC_CNTL_SLP_TIMER0_REG	RTC sleep timer		0x3FF48004	R/W

RTC_CNTL_SLP_TIMER1_REG	RTC sleep timer, alarm and control		0x3FF48008	R/W

RTC_CNTL_TIME_UPDATE_REG	Update control of RTC timer		0x3FF4800C	RO

RTC_CNTL_TIME0_REG	RTC timer low 32 bits		0x3FF48010	RO

RTC_CNTL_TIME1_REG	RTC timer high 16 bits		0x3FF48014	RO

RTC_CNTL_STATE0_REG	RTC sleep, SDIO and ULP control		0x3FF48018	R/W

RTC_CNTL_TIMER1_REG	CPU stall enable		0x3FF4801C	R/W

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Name	Description		Address	Access
RTC_CNTL_TIMER2_REG	Slow clock and touch controller config-		0x3FF48020	R/W
RTC_CNTL_TIMER2_REG	uration		0x3FF48020	R/W
	uration

RTC_CNTL_TIMER5_REG	Minimal sleep cycles in slow clock		0x3FF4802C	R/W

Reset state and wakeup control registers

RTC_CNTL_RESET_STATE_REG	Reset state control and cause of CPUs		0x3FF48034	RO

RTC_CNTL_WAKEUP_STATE_REG	Wake-up filter, enable and cause		0x3FF48038	RO

RTC_CNTL_EXT_WAKEUP_CONF_REG	Configuration of wake-up at low/high		0x3FF48060	R/W
RTC_CNTL_EXT_WAKEUP_CONF_REG	level		0x3FF48060	R/W
	level

RTC_CNTL_EXT_WAKEUP1_REG	Selection of pads for external wake-up		0x3FF480CC	R/W
RTC_CNTL_EXT_WAKEUP1_REG	and wake-up clear bit		0x3FF480CC	R/W
	and wake-up clear bit

RTC_CNTL_EXT_WAKEUP1_STATUS_REG	External wake-up status		0x3FF480D0	RO

RTC interrupt control and status registers

RTC_CNTL_INT_ENA_REG	Interrupt enable bits		0x3FF4803C	R/W

RTC_CNTL_INT_RAW_REG	Raw interrupt status		0x3FF48040	RO

RTC_CNTL_INT_ST_REG	Masked interrupt status		0x3FF48044	RO

RTC_CNTL_INT_CLR_REG	Interrupt clear bits		0x3FF48048	WO

RTC general purpose retention registers

RTC_CNTL_STORE0_REG	General purpose retention register 0		0x3FF4804C	R/W

RTC_CNTL_STORE1_REG	General purpose retention register 1		0x3FF48050	R/W

RTC_CNTL_STORE2_REG	General purpose retention register 2		0x3FF48054	R/W

RTC_CNTL_STORE3_REG	General purpose retention register 3		0x3FF48058	R/W

RTC_CNTL_STORE4_REG	General purpose retention register 4		0x3FF480B0	R/W

RTC_CNTL_STORE5_REG	General purpose retention register 5		0x3FF480B4	R/W

RTC_CNTL_STORE6_REG	General purpose retention register 6		0x3FF480B8	R/W

RTC_CNTL_STORE7_REG	General purpose retention register 7		0x3FF480BC	R/W

Internal power management registers

RTC_CNTL_ANA_CONF_REG	Power-up/down configuration		0x3FF48030	R/W

RTC_CNTL_VREG_REG	Internal power distribution and control		0x3FF4807C	R/W

RTC_CNTL_PWC_REG	RTC domain power management		0x3FF48080	R/W

RTC_CNTL_DIG_PWC_REG	Digital domain power management		0x3FF48084	R/W

RTC_CNTL_DIG_ISO_REG	Digital domain isolation control		0x3FF48088	RO

RTC watchdog configuration and control registers

RTC_CNTL_WDTCONFIG0_REG	WDT Configuration register 0		0x3FF4808C	R/W

RTC_CNTL_WDTCONFIG1_REG	WDT Configuration register 1		0x3FF48090	R/W

RTC_CNTL_WDTCONFIG2_REG	WDT Configuration register 2		0x3FF48094	R/W

RTC_CNTL_WDTCONFIG3_REG	WDT Configuration register 3		0x3FF48098	R/W

RTC_CNTL_WDTCONFIG4_REG	WDT Configuration register 4		0x3FF4809C	R/W

RTC_CNTL_WDTFEED_REG	Watchdog feed register		0x3FF480A0	WO

RTC_CNTL_WDTWPROTECT_REG	Watchdog write protect register		0x3FF480A4	R/W

Miscellaneous RTC configuration registers

RTC_CNTL_EXT_XTL_CONF_REG	XTAL control by external pads		0x3FF4805C	R/W

RTC_CNTL_SLP_REJECT_CONF_REG	Reject cause and enable control		0x3FF48064	R/W

RTC_CNTL_CPU_PERIOD_CONF_REG	CPU period select		0x3FF48068	R/W

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31 Low-Power Management (RTC_CNTL)

Name	Description	Address	Access
RTC_CNTL_CLK_CONF_REG	Configuration of RTC clocks	0x3FF48070	R/W

RTC_CNTL_SDIO_CONF_REG	SDIO configuration	0x3FF48074	R/W

RTC_CNTL_SW_CPU_STALL_REG	Stall of CPUs	0x3FF480AC	R/W

RTC_CNTL_HOLD_FORCE_REG	RTC pad hold register	0x3FF480C8	R/W

RTC_CNTL_BROWN_OUT_REG	Brownout management	0x3FF480D4	R/W

31.5Registers

The addresses in parenthesis besides register names are the register addresses relative to the Low-power Management (RTC) base address provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 31.4 Register Summary.

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31 Low-Power Management (RTC_CNTL)

						NORSTRST
						_	_
			RST		FORCEFORCE
			RST		_	_
		SYS WRAPWRAP
			_
		_	_	_
	SW DG			DG
	_	_	_
CNTLCNTLCNTL						(reserved)
RTC RTC RTC						(reserved)
_	_	_

NOSLEEP

RST

PROCPU APPCPU

FORCEFORCE

FORCEFORCEFOLW

FOLW

FORCEFORCEFOLW

RST

FORCEFORCE

FORCEFORCEI2C

FORCEFORCE

I2C _

PROCPUAPPCPUSTALL

STALL

I2C

CORECORECOREI2C

I2C I2C FORCEFORCESLEEP

BIAS BIAS BIAS BIAS BIAS BIAS BIAS BIAS BIAS XTL

XTL BBPLLBBPLLBBPLLBBPLLBB

CNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTL

CNTL

RTC RTC RTC RTC RTC RTC RTC

RTC RTC RTC RTC RTC

RTC

RTC RTC RTC RTC RTC

RTC

31		30	29	28					23	22	21	20	19		18			17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
																																				Reset

0		0	0	0	0	0	0	0	0	1	0	0	1			0		0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0
	RTC_CNTL_SW_SYS_RST										SW system reset. (WO)
	RTC_CNTL_DG_WRAP_FORCE_NORST The digital core forces no reset in deep sleep. (R/W)
	RTC_CNTL_DG_WRAP_FORCE_RST The digital core can force a reset in deep sleep. (R/W)
	RTC_CNTL_BIAS_CORE_FORCE_PU																BIAS_CORE force power up. (R/W)
	RTC_CNTL_BIAS_CORE_FORCE_PD																BIAS_CORE force power down. (R/W)
	RTC_CNTL_BIAS_CORE_FOLW_8M															BIAS_CORE follow CK8M. (R/W)
	RTC_CNTL_BIAS_I2C_FORCE_PU													BIAS_I2C force power up. (R/W)
	RTC_CNTL_BIAS_I2C_FORCE_PD													BIAS_I2C force power down. (R/W)
	RTC_CNTL_BIAS_I2C_FOLW_8M												BIAS_I2C follow CK8M. (R/W)
	RTC_CNTL_BIAS_FORCE_NOSLEEP																BIAS_SLEEP force no sleep. (R/W)
	RTC_CNTL_BIAS_FORCE_SLEEP													BIAS_SLEEP force sleep. (R/W)
	RTC_CNTL_BIAS_SLEEP_FOLW_8M																BIAS_SLEEP follow CK8M. (R/W)
	RTC_CNTL_XTL_FORCE_PU											Crystal force power up. (R/W)
	RTC_CNTL_XTL_FORCE_PD Crystal force power down. (R/W)
	RTC_CNTL_BBPLL_FORCE_PU												BB_PLL force power up. (R/W)
	RTC_CNTL_BBPLL_FORCE_PD												BB_PLL force power down. (R/W)
	RTC_CNTL_BBPLL_I2C_FORCE_PU															BB_PLL_I2C force power up. (R/W)
	RTC_CNTL_BBPLL_I2C_FORCE_PD															BB_PLL _I2C force power down. (R/W)
	RTC_CNTL_BB_I2C_FORCE_PU												BB_I2C force power up. (R/W)
	RTC_CNTL_BB_I2C_FORCE_PD												BB_I2C force power down. (R/W)
	Continued on the next page...

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31 Low-Power Management (RTC_CNTL)

Continued from the previous page...

RTC_CNTL_SW_PROCPU_RST PRO_CPU SW reset. (WO)

RTC_CNTL_SW_APPCPU_RST APP_CPU SW reset. (WO)

RTC_CNTL_SW_STALL_PROCPU_C0 described under RTC_CNTL_SW_CPU_STALL_REG. (R/W)

RTC_CNTL_SW_STALL_APPCPU_C0 described under RTC_CNTL_SW_CPU_STALL_REG. (R/W)

31	0
		Reset

0x000000000

RTC_CNTL_SLP_TIMER0_REG RTC sleep timer low 32 bits. (R/W)

																	EN
																_
																ALARM
																_
																TIMER			HI
																		_
																_		VAL
																MAIN		_
																MAIN		SLP
																_		_
							(reserved)									CNTL		CNTL
							(reserved)								RTC			RTC
																_		_

31														17	16	15				0
																					Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0			0x00000

RTC_CNTL_MAIN_TIMER_ALARM_EN Timer alarm enable bit. (R/W)

RTC_CNTL_SLP_VAL_HI RTC sleep timer high 16 bits. (R/W)

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31 Low-Power Management (RTC_CNTL)

			UPDATEVALID
			_	_
		TIME TIME
		_	_
	CNTLCNTL																(reserved)
RTC RTC																	(reserved)
	_	_

31	30	59																													30
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_TIME_UPDATE Set 1: to update register with RTC timer. (WO)

RTC_CNTL_TIME_VALID Indicates that the register is updated. (RO)

31																			0
																				Reset

														0x000000000
	RTC_CNTL_TIME0_REG								RTC timer low 32 bits. (RO)
								Register 31.6. RTC_CNTL_TIME1_REG (0x0014)
																		HI
																	_
																	TIME
																	_
								(reserved)									CNTL
								(reserved)									RTC
																	_

31															16	15			0
																				Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0x00000

RTC_CNTL_TIME_HI RTC timer high 16 bits. (RO)

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																		EN		EN
																	_			EN
																TIMER			_
										IND						TIMER
						REJECTWAKEUP				_			CP		_		TIMER
						REJECTWAKEUP							CP				_
					EN			ACTIVE						SLP		SLP
													_			SLP
															_
				_			SLP SDIO				ULP		TOUCH
		SLEEPSLP					SLP SDIO				ULP		TOUCH
					_		_					_
		_	_			_	_				_	_
	CNTLCNTLCNTLCNTL									CNTLCNTL																(reserved)
RTC RTC RTC RTC							(reserved)		RTC RTC																	(reserved)
	_	_	_		_					_	_

31	30	29	28		27			25	24	23	22																										0
																																						Reset

0	0	0	0		0		0	0	0	0	0	0		0		0	0		0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_SLEEP_EN Sleep enable bit. (R/W)

RTC_CNTL_SLP_REJECT Sleep reject bit. (R/W)

RTC_CNTL_SLP_WAKEUP Sleep wake-up bit. (R/W)

RTC_CNTL_SDIO_ACTIVE_IND SDIO active indication. (RO)

RTC_CNTL_ULP_CP_SLP_TIMER_EN ULP coprocessor timer enable bit. (R/W)

RTC_CNTL_TOUCH_SLP_TIMER_EN Touch timer enable bit. (R/W)

																																	EN
																																_
																																STALL
																																_
																																CPU
																																_
															(reserved)																	CNTL
															(reserved)																RTC
																																_

31																														1	0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
	RTC_CNTL_CPU_STALL_EN										CPU stall enable bit. (R/W)

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							WAIT
							_
		_				START
			OFF
			CK8M		_
		_		TOUCH
	TIME			_
	MIN			ULPCP
	_
	_			_
	CNTL			CNTL								(reserved)
	RTC			RTC								(reserved)
	_			_

31	24		23	15	14														0
																				Reset

	0x001			0x010	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_MIN_TIME_CK8M_OFF Minimal amount of cycles in RTC_SLOW_CLK to power down CK8M. (R/W)

RTC_CNTL_ULPCP_TOUCH_START_WAIT Awaited cycles in RTC_SLOW_CLK before ULP coprocessor/touch controller starts working. (R/W)

																		VAL
																	_
																	SLP
																	_
																	MIN
																	_
								(reserved)									CNTL					(reserved)
								(reserved)									RTC					(reserved)
																	_

31															16	15	8	7							0
																										Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0x080	0	0	0	0	0	0	0	0

RTC_CNTL_MIN_SLP_VAL Minimal amount of sleep cycles in RTC_SLOW_CLK. (R/W)

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											PU				PU						PU		PD
											PU				PU						_	_
							_			_				_		PU		PU	FORCEFORCE
					PU		_					PBUSI2C							FORCEFORCE
								I2C							_
																		_
		PLL			_
		PLL		CKGEN					RFRXTXRFPVTMON PLLAPLLA
			I2C								_		_						_	_
		_
		_	_						_		_		_					_	_
	CNTLCNTL					CNTLCNTLCNTL									CNTLCNTL															(reserved)
RTC RTC (reserved)RTC						RTC			RTC (reserved)RTC RTC																					(reserved)
	_	_			_			_			_			_			_

31	30	29	28		27				26		25		24		23			22																							0
																																										Reset

0	0	0	0			0			0		0		0		1			0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_PLL_I2C_PU 1: PLL_I2C power up, otherwise power down. (R/W)

RTC_CNTL_CKGEN_I2C_PU 1: CKGEN_I2C power up, otherwise power down. (R/W)

RTC_CNTL_RFRX_PBUS_PU 1: RFRX_PBUS power up, otherwise power down. (R/W)

RTC_CNTL_TXRF_I2C_PU 1: TXRF_I2C power up, otherwise power down. (R/W)

RTC_CNTL_PVTMON_PU 1: PVTMON power up, otherwise power down. (R/W)

RTC_CNTL_PLLA_FORCE_PU PLLA force power up. (R/W)

RTC_CNTL_PLLA_FORCE_PD PLLA force power down. (R/W)

SEL

APPCPU

PROCPU

VECTORVECTOR

STATSTAT

CAUSE

PROCPUAPPCPU

RESET

(reserved)

CNTLCNTL

RTC

CNTL

RTC

CNTL

RTC RTC

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0

x x

RTC_CNTL_PROCPU_STAT_VECTOR_SEL PRO_CPU state vector selection. (R/W)

RTC_CNTL_APPCPU_STAT_VECTOR_SEL APP_CPU state vector selection. (R/W)

RTC_CNTL_RESET_CAUSE_APPCPU Reset cause for APP_CPU. (RO)

RTC_CNTL_RESET_CAUSE_PROCPU Reset cause for PRO_CPU. (RO)

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															FILTER				ENA			CAUSE
														_					ENA			CAUSE
											GPIO		WAKEUP						_			_
											GPIO						WAKEUP					WAKEUP
												_
											_						_					_
				(reserved)						CNTL						CNTL						CNTL
				(reserved)					RTC						RTC							RTC
										_						_						_

31								23	22	21										11	10	0
																							Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0		0x000

RTC_CNTL_GPIO_WAKEUP_FILTER Enable filter for GPIO wake-up event. (R/W)

RTC_CNTL_WAKEUP_ENA Wake-up enable bitmap. (R/W)

RTC_CNTL_WAKEUP_CAUSE Wake-up cause. (RO)

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31 Low-Power Management (RTC_CNTL)

ENA

ENA _

INT

ENA

INT

ENA _

INT

ENA

TIMER

OUT

REJECTWAKEUP

INT

VALIDINT

IDLE

MAINBROWNTOUCHULP

TIME WDT SDIO SLP

SLP

(reserved)

CNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTL

RTC RTC RTC RTC RTC

RTC

RTC RTC

Reset

RTC_CNTL_MAIN_TIMER_INT_ENA The interrupt enable bit for the RTC_CNTL_MAIN_TIMER_INT interrupt. (R/W)

RTC_CNTL_BROWN_OUT_INT_ENA The interrupt enable bit for the

RTC_CNTL_BROWN_OUT_INT interrupt. (R/W)

RTC_CNTL_TOUCH_INT_ENA The interrupt enable bit for the RTC_CNTL_TOUCH_INT interrupt. (R/W)

RTC_CNTL_ULP_CP_INT_ENA The interrupt enable bit for the RTC_CNTL_ULP_CP_INT interrupt. (R/W)

RTC_CNTL_TIME_VALID_INT_ENA The interrupt enable bit for the RTC_CNTL_TIME_VALID_INT interrupt. (R/W)

RTC_CNTL_WDT_INT_ENA The interrupt enable bit for the RTC_CNTL_WDT_INT interrupt. (R/W)

RTC_CNTL_SDIO_IDLE_INT_ENA The interrupt enable bit for the RTC_CNTL_SDIO_IDLE_INT interrupt. (R/W)

RTC_CNTL_SLP_REJECT_INT_ENA The interrupt enable bit for the RTC_CNTL_SLP_REJECT_INT interrupt. (R/W)

RTC_CNTL_SLP_WAKEUP_INT_ENA The interrupt enable bit for the

RTC_CNTL_SLP_WAKEUP_INT interrupt. (R/W)

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RAW

RAW_

RAW

RAW_

RAW

INT

RAW_

INT

RAW

TIMER

OUT

REJECTWAKEUP

INT

VALIDINT IDLE

MAINBROWNTOUCHULP

TIME WDT SDIO SLP

SLP

(reserved)

CNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTL

RTC RTC RTC RTC RTC

RTC

Reset

RTC_CNTL_MAIN_TIMER_INT_RAW The raw interrupt status bit for the

RTC_CNTL_MAIN_TIMER_INT interrupt. (RO)

RTC_CNTL_BROWN_OUT_INT_RAW The raw interrupt status bit for the

RTC_CNTL_BROWN_OUT_INT interrupt. (RO)

RTC_CNTL_TOUCH_INT_RAW The raw interrupt status bit for the RTC_CNTL_TOUCH_INT interrupt. (RO)

RTC_CNTL_ULP_CP_INT_RAW The raw interrupt status bit for the RTC_CNTL_ULP_CP_INT interrupt. (RO)

RTC_CNTL_TIME_VALID_INT_RAW The raw interrupt status bit for the

RTC_CNTL_TIME_VALID_INT interrupt. (RO)

RTC_CNTL_WDT_INT_RAW The raw interrupt status bit for the RTC_CNTL_WDT_INT interrupt. (RO)

RTC_CNTL_SDIO_IDLE_INT_RAW The raw interrupt status bit for the RTC_CNTL_SDIO_IDLE_INT interrupt. (RO)

RTC_CNTL_SLP_REJECT_INT_RAW The raw interrupt status bit for the

RTC_CNTL_SLP_REJECT_INT interrupt. (RO)

RTC_CNTL_SLP_WAKEUP_INT_RAW The raw interrupt status bit for the

RTC_CNTL_SLP_WAKEUP_INT interrupt. (RO)

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INT

TIMER

OUT

INT

REJECTWAKEUP

INT

VALIDINT IDLE

SLP

MAINBROWNTOUCHSAR TIME WDT SDIO SLP

(reserved)

CNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTL

RTC RTC RTC RTC RTC

RTC

RTC RTC

Reset

RTC_CNTL_MAIN_TIMER_INT_ST The masked interrupt status bit for the

RTC_CNTL_MAIN_TIMER_INT interrupt. (RO)

RTC_CNTL_BROWN_OUT_INT_ST The masked interrupt status bit for the

RTC_CNTL_BROWN_OUT_INT interrupt. (RO)

RTC_CNTL_TOUCH_INT_ST The masked interrupt status bit for the RTC_CNTL_TOUCH_INT interrupt. (RO)

RTC_CNTL_SAR_INT_ST The masked interrupt status bit for the RTC_CNTL_SAR_INT interrupt. (RO)

RTC_CNTL_TIME_VALID_INT_ST The masked interrupt status bit for the

RTC_CNTL_TIME_VALID_INT interrupt. (RO)

RTC_CNTL_WDT_INT_ST The masked interrupt status bit for the RTC_CNTL_WDT_INT interrupt. (RO)

RTC_CNTL_SDIO_IDLE_INT_ST The masked interrupt status bit for the

RTC_CNTL_SDIO_IDLE_INT interrupt. (RO)

RTC_CNTL_SLP_REJECT_INT_ST The masked interrupt status bit for the

RTC_CNTL_SLP_REJECT_INT interrupt. (RO)

RTC_CNTL_SLP_WAKEUP_INT_ST The masked interrupt status bit for the

RTC_CNTL_SLP_WAKEUP_INT interrupt. (RO)

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31 Low-Power Management (RTC_CNTL)

CLR

CLR _

INT

CLR

INT

CLR

INT

REJECTWAKEUP

TIMER

OUT

INT

CLR

VALIDINT IDLE

MAINBROWNTOUCHSAR

TIME WDT SDIO SLP

SLP

(reserved)

CNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTL

RTC RTC RTC RTC RTC

RTC

Reset

RTC_CNTL_MAIN_TIMER_INT_CLR Set this bit to clear the RTC_CNTL_MAIN_TIMER_INT interrupt. (WO)

RTC_CNTL_BROWN_OUT_INT_CLR Set this bit to clear the RTC_CNTL_BROWN_OUT_INT interrupt. (WO)

RTC_CNTL_TOUCH_INT_CLR Set this bit to clear the RTC_CNTL_TOUCH_INT interrupt. (WO)

RTC_CNTL_SAR_INT_CLR Set this bit to clear the RTC_CNTL_SAR_INT interrupt. (WO)

RTC_CNTL_TIME_VALID_INT_CLR Set this bit to clear the RTC_CNTL_TIME_VALID_INT interrupt. (WO)

RTC_CNTL_WDT_INT_CLR Set this bit to clear the RTC_CNTL_WDT_INT interrupt. (WO)

RTC_CNTL_SDIO_IDLE_INT_CLR Set this bit to clear the RTC_CNTL_SDIO_IDLE_INT interrupt. (WO)

RTC_CNTL_SLP_REJECT_INT_CLR Set this bit to clear the RTC_CNTL_SLP_REJECT_INT interrupt. (WO)

RTC_CNTL_SLP_WAKEUP_INT_CLR Set this bit to clear the RTC_CNTL_SLP_WAKEUP_INT interrupt. (WO)

31	0
		Reset

x x x x x x x x x x x x x x x x	x x x x x x x x x x x x x x x x

RTC_CNTL_STOREn_REG 32-bit general-purpose retention register. (R/W)

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31 Low-Power Management (RTC_CNTL)

										_										WAKEUP
										IN	IDEL								_
									_										FOR
								STATE										_
							_											RDY
							MAIN										_
							MAIN										RTC
						_										_
		(reserved)		RTC	CNTL			(reserved)							CNTL									(reserved)
		(reserved)		RTC				(reserved)						RTC										(reserved)
				_											_

31			28	27	26								20	19	18																		0
																																		Reset

0	0	0	0	0	0	0	0	0		0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_RTC_RDY_FOR_WAKEUP Indicates the RTC is ready to be triggered by any wakeup source. (RO)

RTC_CNTL_MAIN_STATE_IN_IDLE Indicates the RTC state.

•0: the chip can be either

–in sleep modes.

–entering sleep modes. In this case, wait until RTC_CNTL_RTC_RDY_FOR_WAKEUP bit is set, then you can wake up the chip.

–exiting sleep mode. In this case, RTC_CNTL_MAIN_STATE_IN_IDLE will eventually become 1.

•1: the chip is not in sleep modes (i.e. running normally).

								EN		LV
							_		_
						CTR		CTR
					_		_
				EXT		EXT
			_			_
		XTL			XTL
		_		_
	CNTLCNTL																				(reserved)
RTC RTC																					(reserved)
	_	_

31	30	29																																	0
																																				Reset

0	0	0	0			0		0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_XTL_EXT_CTR_EN Enable control XTAL with external pads. (R/W)

RTC_CNTL_XTL_EXT_CTR_LV 0: power down XTAL at high level, 1: power down XTAL at low level. (R/W)

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31 Low-Power Management (RTC_CNTL)

						LV		LV
						_	_
				WAKEUP1WAKEUP0
			_		_
		EXT			EXT
		_		_
	CNTLCNTL																		(reserved)
RTC RTC																			(reserved)
	_	_

31	30	29																															0
																																		Reset

0	0	0	0		0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_EXT_WAKEUP1_LV 0: external wake-up at low level, 1: external wake-up at high level. (R/W)

RTC_CNTL_EXT_WAKEUP0_LV 0: external wake-up at low level, 1: external wake-up at high level. (R/W)

														EN			EN
														EN	_
													_
													REJECT
						CAUSE					REJECT					EN			EN
						CAUSE			_						_			_
								_				SLP	REJECTREJECT
						_			SLP			SLP
				REJECT			DEEPLIGHTSDIO GPIO
												_		_
			_				_	_	_			_
		RTC	CNTL			CNTLCNTLCNTLCNTL																					(reserved)
		RTC			RTC RTC RTC RTC																						(reserved)
		_				_	_	_	_

31			28		27	26	25	24		23																												0
																																							Reset

0	0	0	0		0	0	0	0		0		0	0		0				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_REJECT_CAUSE Sleep reject cause. (RO)

RTC_CNTL_DEEP_SLP_REJECT_EN Enable reject for deep sleep. (R/W)

RTC_CNTL_LIGHT_SLP_REJECT_EN Enable reject for light sleep. (R/W)

RTC_CNTL_SDIO_REJECT_EN Enable SDIO reject. (R/W)

RTC_CNTL_GPIO_REJECT_EN Enable GPIO reject. (R/W)

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							Register 31.23. RTC_CNTL_CPU_PERIOD_CONF_REG (0x0068)
								SEL
							_
					CPUPERIOD
			RTC				CONF
			RTC		CPUSEL
				_
		_			_
	CNTL			CNTL														(reserved)
	RTC	RTC																(reserved)
	_		_

31	30	29		28																												0
																																	Reset

0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_RTC_CPUPERIOD_SEL CPU period selection. (R/W)

RTC_CNTL_CPUSEL_CONF CPU selection option. (R/W)

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31 Low-Power Management (RTC_CNTL)

SEL

D256 _

RTC

CLK

SEL

FORCEFORCE

DFREQ

SEL

DIV

CLK8MCLK8MXTAL32K

DIV

CLK

FAST

CLK

CK8MCK8M

ANA

RTC

SOC

CK8MCK8M

CK8M

DIG

DIG DIG

ENB ENB

CK8M

CNTL

CNTLCNTL

CNTL

(reserved)

CNTL

CNTLCNTLCNTLCNTLCNTL

CNTL

(reserved)

RTC

RTC RTC

RTC

(reserved)RTC RTC RTC

RTC RTC

RTC

Reset

RTC_CNTL_ANA_CLK_RTC_SEL RTC_SLOW_CLK sel. 0: RC_SLOW_CLK, 1: XTL32K_CLK, 2: RC_FAST_DIV_CLK. (R/W)

RTC_CNTL_RTC_FAST_CLK_SEL RTC_FAST_CLK sel. 0: XTAL div 4, 1: CK8M. (R/W)

RTC_CNTL_SOC_CLK_SEL SoC clock selection. 0: XTAL, 1: PLL, 2: CK8M, 3: APLL. (R/W)

RTC_CNTL_CK8M_FORCE_PU CK8M force power up. (R/W)

RTC_CNTL_CK8M_FORCE_PD CK8M force power down. (R/W)

RTC_CNTL_CK8M_DFREQ CK8M_DFREQ. (R/W)

RTC_CNTL_CK8M_DIV_SEL Divider = reg_rtc_cntl_ck8m_div_sel + 1. (R/W)

RTC_CNTL_DIG_CLK8M_EN Enable CK8M for digital core (no relation to RTC core). (R/W)

RTC_CNTL_DIG_CLK8M_D256_EN Enable RC_FAST_DIV_CLK for digital core (no relation to RTC core). (R/W)

RTC_CNTL_DIG_XTAL32K_EN Enable XTL32K_CLK for digital core (no relation to RTC core). (R/W)

RTC_CNTL_ENB_CK8M_DIV 1: RC_FAST_DIV_CLK is actually CK8M, 0: RC_FAST_DIV_CLK is CK8M divided by 256. (R/W)

RTC_CNTL_ENB_CK8M Disable CK8M and RC_FAST_DIV_CLK. (R/W)

RTC_CNTL_CK8M_DIV RC_FAST_DIV_CLK divider. 00: div128, 01: div256, 10: div512, 11: div1024. (R/W)

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31 Low-Power Management (RTC_CNTL)

													Register 31.25. RTC_CNTL_SDIO_CONF_REG (0x0074)
																									EN
							VREG												READY					_
							VREG																_
							_						SDIO											PD
									SDIO											TIEH FORCEVREG				PD
									SDIO								_		_
								_					_				_
					SDIO						DREFM								_	_	_
			XPD				DREFH				DREFM				DREFL REG1P8SDIO SDIO SDIO
				_
		_				_				_				_			_	_	_	_
	CNTL			CNTL				CNTL				CNTL				CNTLCNTLCNTLCNTL														(reserved)
RTC		RTC				RTC				RTC			RTC RTC RTC RTC																	(reserved)
	_		_				_				_				_		_	_	_

31	30		29		28		27		26		25		24			23	22	21	20																					0
																																									Reset

0	0		0		0		0		0		1		0			1	0	1	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_XPD_SDIO_VREG SW option for XPD_SDIO_VREG; active only when reg_rtc_cntl_sdio_force == 1. (R/W)

RTC_CNTL_DREFH_SDIO SW option for DREFH_SDIO; active only when reg_rtc_cntl_sdio_force == 1. (R/W)

RTC_CNTL_DREFM_SDIO SW option for DREFM_SDIO; active only when reg_rtc_cntl_sdio_force == 1. (R/W)

RTC_CNTL_DREFL_SDIO SW option for DREFL_SDIO; active only when reg_rtc_cntl_sdio_force == 1. (R/W)

RTC_CNTL_REG1P8_READY Read-only register for REG1P8_READY. (RO)

RTC_CNTL_SDIO_TIEH SW option for SDIO_TIEH; active only when reg_rtc_cntl_sdio_force == 1. (R/W)

RTC_CNTL_SDIO_FORCE 1: use SW option to control SDIO_VREG; 0: use state machine to control SDIO_VREG. (R/W)

RTC_CNTL_SDIO_VREG_PD_EN Power down SDIO_VREG in sleep; active only when reg_rtc_cntl_sdio_force == 0. (R/W)

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31 Low-Power Management (RTC_CNTL)

WAK

SLP

DBIAS

FORCEFORCE

WAK

SLP

DCAP

VREG

DBIAS

PREGPREGDBOOSTDBOOST DBIAS

SCK

DIG

CNTLCNTLCNTLCNTL

CNTL

(reserved)

RTC RTC RTC RTC

RTC

Reset

RTC_CNTL_VREG_FORCE_PU RTC voltage regulator - force power up. (R/W)

RTC_CNTL_VREG_FORCE_PD RTC voltage regulator - force power down (in this case power down means decreasing the voltage to 0.8V or lower). (R/W)

RTC_CNTL_DBOOST_FORCE_PU RTC_DBOOST force power up. (R/W)

RTC_CNTL_DBOOST_FORCE_PD RTC_DBOOST force power down. (R/W)

RTC_CNTL_DBIAS_WAK RTC_DBIAS during wake-up. (R/W)

RTC_CNTL_DBIAS_SLP RTC_DBIAS during sleep. (R/W)

RTC_CNTL_SCK_DCAP Used to adjust the frequency of RTC slow clock. (R/W)

RTC_CNTL_DIG_VREG_DBIAS_WAK Digital voltage regulator DBIAS during wake-up. (R/W)

RTC_CNTL_DIG_VREG_DBIAS_SLP Digital voltage regulator DBIAS during sleep. (R/W)

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31 Low-Power Management (RTC_CNTL)

LPU

LPD

CPU LPU LPD

ISO

NOISO

CPU

ISO

FORCEFORCE

FORCEFORCEFOLW

FORCEFORCE

FORCEFORCEFOLW

NOISOISO

PD FORCEFORCESLOWMEMSLOWMEMSLOWMEMFASTMEMFASTMEMFASTMEMSLOWMEMSLOWMEMSLOWMEMFASTMEMFASTMEMFASTMEMFORCEFORCESLOWMEMSLOWMEMFASTMEMFASTMEM

(reserved)

CNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTL

RTC RTC RTC RTC RTC RTC RTC RTC RTC

RTC RTC

RTC RTC RTC RTC RTC

RTC

RTC RTC

Reset

RTC_CNTL_PD_EN Enable power down rtc_peri in sleep. (R/W)

RTC_CNTL_FORCE_PU rtc_peri force power up. (R/W)

RTC_CNTL_FORCE_PD rtc_peri force power down. (R/W)

RTC_CNTL_SLOWMEM_PD_EN Enable power down RTC memory in sleep. (R/W)

RTC_CNTL_SLOWMEM_FORCE_PU RTC memory force power up. (R/W)

RTC_CNTL_SLOWMEM_FORCE_PD RTC memory force power down. (R/W)

RTC_CNTL_FASTMEM_PD_EN Enable power down fast RTC memory in sleep. (R/W)

RTC_CNTL_FASTMEM_FORCE_PU Fast RTC memory force power up. (R/W)

RTC_CNTL_FASTMEM_FORCE_PD Fast RTC memory force power down. (R/W)

RTC_CNTL_SLOWMEM_FORCE_LPU RTC memory force power up in low-power mode. (R/W)

RTC_CNTL_SLOWMEM_FORCE_LPD RTC memory force power down in low-power mode. (R/W)

RTC_CNTL_SLOWMEM_FOLW_CPU 1: RTC memory low-power mode PD following CPU; 0: RTC memory low-power mode PD following RTC state machine. (R/W)

RTC_CNTL_FASTMEM_FORCE_LPU Fast RTC memory force power up in low-power mode. (R/W)

RTC_CNTL_FASTMEM_FORCE_LPD Fast RTC memory force power down in low-power mode. (R/W)

RTC_CNTL_FASTMEM_FOLW_CPU 1: Fast RTC memory low-power mode PD following CPU; 0: fast RTC memory low-power mode PD following RTC state machine. (R/W)

RTC_CNTL_FORCE_NOISO rtc_peri force no isolation. (R/W)

RTC_CNTL_FORCE_ISO rtc_peri force isolation. (R/W)

RTC_CNTL_SLOWMEM_FORCE_ISO RTC memory force isolation. (R/W)

RTC_CNTL_SLOWMEM_FORCE_NOISO RTC memory force no isolation. (R/W)

RTC_CNTL_FASTMEM_FORCE_ISO Fast RTC memory force isolation. (R/W)

RTC_CNTL_FASTMEM_FORCE_NOISO Fast RTC memory force no isolation. (R/W)

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31 Low-Power Management (RTC_CNTL)

PU PD

FORCEFORCEFORCEFORCEFORCEFORCEFORCEFORCEFORCEFORCE

FORCEFORCE

PU PD

RAM4RAM3RAM2RAM1RAM0PD

FORCEFORCE

RAM4RAM4RAM3RAM3RAM2RAM2RAM1RAM1RAM0RAM0FORCEFORCE

MEM MEM

WRAP

WRAPWRAP

WIFI INTERINTERINTERINTERINTERROM0

WIFI WIFI INTERINTERINTERINTERINTERINTERINTERINTERINTERINTERROM0ROM0LSLPLSLP

CNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTL

RTC

CNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTL

RTC RTC RTC

RTC RTC

RTC RTC RTC

(reserved)

RTC RTC

RTC

RTC RTC RTC RTC

RTC RTC

RTC

(reserved)

Reset

RTC_CNTL_DG_WRAP_PD_EN Enable power down digital core in sleep mode. (R/W)

RTC_CNTL_WIFI_PD_EN Enable power down Wi-Fi in sleep. (R/W)

RTC_CNTL_INTER_RAM4_PD_EN Enable power down internal SRAM 4 in sleep mode. (R/W)

RTC_CNTL_INTER_RAM3_PD_EN Enable power down internal SRAM 3 in sleep mode. (R/W)

RTC_CNTL_INTER_RAM2_PD_EN Enable power down internal SRAM 2 in sleep mode. (R/W)

RTC_CNTL_INTER_RAM1_PD_EN Enable power down internal SRAM 1 in sleep mode. (R/W)

RTC_CNTL_INTER_RAM0_PD_EN Enable power down internal SRAM 0 in sleep mode. (R/W)

RTC_CNTL_ROM0_PD_EN Enable power down ROM in sleep mode. (R/W)

RTC_CNTL_DG_WRAP_FORCE_PU Digital core force power up. (R/W)

RTC_CNTL_DG_WRAP_FORCE_PD Digital core force power down. (R/W)

RTC_CNTL_WIFI_FORCE_PU Wi-Fi force power up. (R/W)

RTC_CNTL_WIFI_FORCE_PD Wi-Fi force power down. (R/W)

RTC_CNTL_INTER_RAM4_FORCE_PU Internal SRAM 4 force power up. (R/W)

RTC_CNTL_INTER_RAM4_FORCE_PD Internal SRAM 4 force power down. (R/W)

RTC_CNTL_INTER_RAM3_FORCE_PU Internal SRAM 3 force power up. (R/W)

RTC_CNTL_INTER_RAM3_FORCE_PD Internal SRAM 3 force power down. (R/W)

RTC_CNTL_INTER_RAM2_FORCE_PU Internal SRAM 2 force power up. (R/W)

RTC_CNTL_INTER_RAM2_FORCE_PD Internal SRAM 2 force power down. (R/W)

RTC_CNTL_INTER_RAM1_FORCE_PU Internal SRAM 1 force power up. (R/W)

RTC_CNTL_INTER_RAM1_FORCE_PD Internal SRAM 1 force power down. (R/W)

RTC_CNTL_INTER_RAM0_FORCE_PU Internal SRAM 0 force power up. (R/W)

RTC_CNTL_INTER_RAM0_FORCE_PD Internal SRAM 0 force power down. (R/W)

RTC_CNTL_ROM0_FORCE_PU ROM force power up. (R/W)

Continued on the next page...

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Continued from the previous page...

RTC_CNTL_ROM0_FORCE_PD ROM force power down. (R/W)

RTC_CNTL_LSLP_MEM_FORCE_PU Memories in digital core force power up in sleep mode. (R/W)

RTC_CNTL_LSLP_MEM_FORCE_PD Memories in digital core force power down in sleep mode. (R/W)

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31 Low-Power Management (RTC_CNTL)

AUTOHOLD

AUTOHOLDPAD

NOISOISO NOISOISO NOISOISO NOISOISO

NOISOISO

HOLDUNHOLDISO

NOISODG

NOISOISO

PAD _

CNTL

FORCEFORCE

NOISOISO

FORCEFORCEFORCEFORCEFORCEFORCEFORCEFORCEFORCEFORCE

AUTOHOLD

FORCEFORCEFORCEFORCE

WRAPWRAP

FORCEFORCE

RAM4RAM4RAM3RAM3RAM2RAM2RAM1RAM1RAM0RAM0FORCEFORCE

RTC

REG

PAD

PAD PAD _

PAD

DG WIFI WIFI INTERINTERINTERINTERINTERINTERINTERINTERINTERINTERROM0ROM0DG

DG REG CLR

CNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTL

(reserved)

RTC RTC RTC

RTC RTC RTC RTC RTC

RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC

RTC

RTC RTC

Reset

RTC_CNTL_DG_WRAP_FORCE_NOISO Digital core force no isolation. (R/W)

RTC_CNTL_DG_WRAP_FORCE_ISO Digital core force isolation. (R/W)

RTC_CNTL_WIFI_FORCE_NOISO Wi-Fi force no isolation. (R/W)

RTC_CNTL_WIFI_FORCE_ISO Wi-Fi force isolation. (R/W)

RTC_CNTL_INTER_RAM4_FORCE_NOISO Internal SRAM 4 force no isolation. (R/W)

RTC_CNTL_INTER_RAM4_FORCE_ISO Internal SRAM 4 force isolation. (R/W)

RTC_CNTL_INTER_RAM3_FORCE_NOISO Internal SRAM 3 force no isolation. (R/W)

RTC_CNTL_INTER_RAM3_FORCE_ISO Internal SRAM 3 force isolation. (R/W)

RTC_CNTL_INTER_RAM2_FORCE_NOISO Internal SRAM 2 force no isolation. (R/W)

RTC_CNTL_INTER_RAM2_FORCE_ISO Internal SRAM 2 force isolation. (R/W)

RTC_CNTL_INTER_RAM1_FORCE_NOISO Internal SRAM 1 force no isolation. (R/W)

RTC_CNTL_INTER_RAM1_FORCE_ISO Internal SRAM 1 force isolation. (R/W)

RTC_CNTL_INTER_RAM0_FORCE_NOISO Internal SRAM 0 force no isolation. (R/W)

RTC_CNTL_INTER_RAM0_FORCE_ISO Internal SRAM 0 force isolation. (R/W)

RTC_CNTL_ROM0_FORCE_NOISO ROM force no isolation. (R/W)

RTC_CNTL_ROM0_FORCE_ISO ROM force isolation. (R/W)

RTC_CNTL_DG_PAD_FORCE_HOLD Digital pad force hold. (R/W)

RTC_CNTL_DG_PAD_FORCE_UNHOLD Digital pad force un-hold. (R/W)

RTC_CNTL_DG_PAD_FORCE_ISO Digital pad force isolation. (R/W)

RTC_CNTL_DG_PAD_FORCE_NOISO Digital pad force no isolation. (R/W)

Continued on the next page...

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Continued from the previous page...

RTC_CNTL_REG_RTC_CNTL_DG_PAD_AUTOHOLD_EN Digital pad enable auto-hold. (R/W)

RTC_CNTL_CLR_REG_RTC_CNTL_DG_PAD_AUTOHOLD Write-only register clears digital pad auto-hold. (WO)

RTC_CNTL_DG_PAD_AUTOHOLD Read-only register indicates digital pad auto-hold status. (RO)

LENGTH

MOD

STG0

STG1

STG2

STG3

CPU

SYS

RESETRESETSLP

FLASHBOOTPROCPUAPPCPUPAUSE

RESET

WDT

WDT WDT WDT WDT

CNTL

CNTLCNTLCNTLCNTL

reserved

RTC

reservedreserved

RTC

RTC RTC RTC

Reset

RTC_CNTL_WDT_PAUSE_IN_SLP Pause RTC WDT in sleep. (R/W)

RTC_CNTL_WDT_APPCPU_RESET_EN RTC WDT reset APP_CPU enable. (R/W)

RTC_CNTL_WDT_PROCPU_RESET_EN RTC WDT reset PRO_CPU enable. (R/W)

RTC_CNTL_WDT_FLASHBOOT_MOD_EN Enable RTC WDT in flash boot. (R/W)

RTC_CNTL_WDT_SYS_RESET_LENGTH System reset counter length, unit: RTC_SLOW_CLK cycle. The value can be 0 ~ 7. (R/W)

RTC_CNTL_WDT_CPU_RESET_LENGTH CPU reset counter length, unit: RTC_SLOW_CLK cycle. The value can be 0 ~ 7. (R/W)

RTC_CNTL_WDT_STG3 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage enable, 4: RTC reset stage enable. (R/W)

RTC_CNTL_WDT_STG2 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage enable, 4: RTC reset stage enable. (R/W)

RTC_CNTL_WDT_STG1 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage enable, 4: RTC reset stage enable. (R/W)

RTC_CNTL_WDT_STG0 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage enable, 4: RTC reset stage enable. (R/W)

RTC_CNTL_WDT_EN Enable RTC WDT. (R/W)

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31 Low-Power Management (RTC_CNTL)

31	0
		Reset

0x000000FFF

RTC_CNTL_WDTCONFIGn_REG Hold cycles for WDT stage n. (R/W)

				FEED
			_
			WDT
		_
	CNTL															(reserved)
RTC																(reserved)
	_

31	30																														0
																																Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_WDT_FEED SW feeds WDT. (WO)

31	0
		Reset

0x050D83AA1

RTC_CNTL_WDTWPROTECT_REG If RTC_CNTL_WDTWPROTECT is other than 0x50d83aa1, then the RTC watchdog will be in a write-protected mode and RTC_CNTL_WDTCONFIGn_REG will be locked for modifications. (R/W)

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										C1							C1
									_							_
							PROCPU							APPCPU
							_							_
						STALL							STALL
					_							_
					SW							SW
					_						_
			RTC	CNTL					RTC		CNTL													(reserved)
			_							_

31					26	25						20	19																				0
																																		Reset

0	0	0	0	0	0	0	0	0		0	0	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

RTC_CNTL_SW_STALL_PROCPU_C1 reg_rtc_cntl_sw_stall_procpu_c1[5:0], reg_rtc_cntl_sw_stall_procpu_c0[1:0] == 0x86 (100001 10) will stall PRO_CPU, see also RTC_CNTL_OPTIONS0_REG. (R/W)

RTC_CNTL_SW_STALL_APPCPU_C1 reg_rtc_cntl_sw_stall_appcpu_c1[5:0], reg_rtc_cntl_sw_stall_appcpu_c0[1:0] == 0x86 (100001 10) will stall APP_CPU, see also RTC_CNTL_OPTIONS0_REG. (R/W)

31	0
		Reset

x x x x x x x x x x x x x x x x	x x x x x x x x x x x x x x x x

RTC_CNTL_STOREn_REG 32-bit general-purpose retention register. (R/W)

Espressif Systems

717

ESP32 TRM (Version 5.0)

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31 Low-Power Management (RTC_CNTL)

FORCEFORCEFORCEFORCEFORCEFORCEFORCEFORCE

FORCEFORCEFORCEFORCE

FORCEFORCE

HOLDHOLDHOLDHOLDHOLDHOLDHOLDHOLD_

FORCEFORCE

PAD7PAD6PAD5PAD4PAD3PAD2PAD1PAD0 HOLDHOLDHOLDHOLD

HOLDHOLD

X32NX32P TOUCHTOUCHTOUCHTOUCHTOUCHTOUCHTOUCHTOUCHSENSE4SENSE3SENSE2SENSE1PDAC2PDAC1ADC2ADC1

(reserved)

CNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTLCNTL

RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC

Reset

RTC_CNTL_X32N_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_X32P_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD7_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD6_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD5_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD4_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD3_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD2_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD1_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD0_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_SENSE4_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_SENSE3_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_SENSE2_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_SENSE1_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_PDAC2_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_PDAC1_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_ADC2_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_ADC1_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

Espressif Systems

718

ESP32 TRM (Version 5.0)

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31 Low-Power Management (RTC_CNTL)

														CLR
														_
														STATUS	SEL
														_	_
														WAKEUP1	WAKEUP1
														_	_
														EXT	EXT
														_	_
						(reserved)								CNTL	CNTL
						(reserved)							RTC		RTC
														_	_

31												19	18	17		0
																	Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0		0

RTC_CNTL_EXT_WAKEUP1_STATUS_CLR Clear external wakeup1 status. (WO)

RTC_CNTL_EXT_WAKEUP1_SEL Bitmap to select RTC pads for external wakeup1. (R/W)

															STATUS
															_
															WAKEUP1
															_
															EXT
															_
							(reserved)								CNTL
							(reserved)								RTC
															_

31													18	17		0
																	Reset

0	0	0	0	0	0	0	0	0	0	0	0	0	0		0

RTC_CNTL_EXT_WAKEUP1_STATUS External wakeup1 status. (RO)

Espressif Systems

719

ESP32 TRM (Version 5.0)

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31 Low-Power Management (RTC_CNTL)

ENA

THRES

ENA

WAIT

ENA

FLASH

DET ENA

RST

OUT

OUT OUT

OUT

OUT OUT

BROWNBROWN

DBROWN BROWN

BROWN

BROWNBROWN

CNTLCNTL

CNTL

CNTLCNTL

(reserved)

RTC RTC

RTC

RTC RTC

Reset

0x2

0x3FF

0 0

0 0 0 0 0 0 0 0

RTC_CNTL_BROWN_OUT_DET Brownout detect. (RO)

RTC_CNTL_BROWN_OUT_ENA Enables brownout. (R/W)

RTC_CNTL_DBROWN_OUT_THRES Brownout threshold. The brownout detector will reset the chip when the supply voltage is approximately below this level. Note that there may be some variation of brownout voltage level between each ESP32 chip. 0: 2.43 V ± 0.05; 1: 2.48 V ± 0.05; 2: 2.58 V ± 0.05; 3: 2.62 V ± 0.05; 4: 2.67 V ± 0.05; 5: 2.70 V ± 0.05; 6: 2.77 V ± 0.05; 7: 2.80 V ± 0.05. (R/W)

RTC_CNTL_BROWN_OUT_RST_ENA Enables brownout reset. (R/W)

RTC_CNTL_BROWN_OUT_RST_WAIT Brownout reset wait cycles. (R/W)

RTC_CNTL_BROWN_OUT_PD_RF_ENA Enables power down RF when brownout happens. (R/W)

RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA Sends suspend command to flash when brownout happens. (R/W)

Espressif Systems

720

ESP32 TRM (Version 5.0)

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