31 Low-Power Management (RTC_CNTL)

Notes*:

1.The power-domain RTC core is the “always-on” power domain, and the FPU/FPD option is not available.

2.The power-domain RTC peripherals include most of the fast logic in RTC, including the ULP co-processor, sensor controllers, etc.

3.The power-domain RTC slow memory should be forced to power on when it is used as retention memory, or when the ULP co-processor is working.

4.The power-domain RTC fast memory should be forced to power on, when it is used as retention memory.

5.When the power-domain digital core is powered down, all included in power domains are powered down.

6.The power-domain Wi-Fi includes the Wi-Fi MAC and BB.

7.Each internal SRAM can be power-gated independently.

31.3.9 Predefined Power Modes

In ESP32, we recommend that you always use the predefined power modes first, before trying to tune each power

control signal. The predefined power modes should cover most scenarios:

•Active mode

–The CPU is clocked at XTAL_DIV_N (40 MHz/26 MHz) or PLL (80 MHz/160 MHz/240 MHz).

–The chip can receive, transmit, or listen.

•Modem-sleep mode

–The CPU is operational and the clock is configurable.

–The Wi-Fi/Bluetooth baseband is clock-gated or powered down. The radio is turned off.

–Current consumption: 30 mA with 80 MHz PLL.

–Current consumption: 3 mA with 2 MHz XTAL.

–Immediate wake-up.

•Light-sleep mode

–The internal 8 MHz oscillator, 40 MHz high-speed crystal, PLL, and radio are disabled.

–The clock in the digital core is gated. The CPUs are stalled.

–The ULP coprocessor and touch controller can be periodically triggered by monitor sensors.

–Current consumption: 800 µA.

–Wake-up latency: less than 1 ms.

•Deep-sleep mode

–The internal 8 MHz oscillator, 40 MHz high-speed crystal, PLL and radio are disabled.

–The digital core is powered down. The CPU context is lost.

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31Low-Power Management (RTC_CNTL)

–The supply voltage to the RTC core drops to 0.7V.

–8 x 32 bits of data are kept in general-purpose retention registers.

–The RTC memory and fast RTC memory can be retained.

–Current consumption: 6.5 µA.

–Wake-up latency: less than 1 ms.

–Recommended for ultra-low-power infrequently-connected Wi-Fi/Bluetooth applications.

•Hibernatation mode

–The internal 8 MHz oscillator, 40 MHz high-speed crystal, PLL, and radio are disabled.

–The digital core is powered down. The CPU context is lost.

–The RTC peripheral domain is powered down.

–The supply voltage to the RTC core drops to 0.7V.

–8 x 32 bits of data are kept in general-purpose retention registers.

–The RTC memory and fast RTC memory are powered down.

–Current consumption: 4.5 µA.

–Wake-up source: RTC timer only.

–Wake-up latency: less than 1 ms.

–Recommended for ultra-low-power infrequently-connected Wi-Fi/Bluetooth applications.

Figure 31­10. Power Modes

By default, the ESP32 is in active mode after a system reset.There are several low-power modes for saving power when the CPU does not need to be kept running, for example, when waiting for an external event. It is up to the

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31 Low-Power Management (RTC_CNTL)

user to select the mode that best balances power consumption, wake-up latency and available wake-up sources. For details, please see Figure 31-10.

Please note that the predefined power mode could be further optimized and adapted to any application.

31.3.10 Wakeup Source

The ESP32 supports various wake-up sources, which could wake up the CPU in different sleep modes. The wake-up source is determined by RTC_CNTL_WAKEUP_ENA, as shown in Table 31-2.

Table 31­2. Wake­up Source

1All wakeup sources can also be configured as the causes to reject sleep, except UART.

2EXT0 can only wake up the chip in light-sleep/deep-sleep mode.

If RTC_CNTL_EXT_WAKEUP0_LV is 1, it is pad high-level triggered; otherwise, it is

low-level triggered. Users can set RTCIO_EXT_WAKEUP0_SEL[4:0] to select one of the RTC PADs to be the wake-up source.

3EXT1 is especially designed to wake up the chip from any sleep mode, and it also supports multiple pads’ combinations.

First, RTC_CNTL_EXT_WAKEUP1_SEL[17:0] should be configured with the bitmap of PADS selected as a wake-up source. Then, if RTC_CNTL_EXT_WAKEUP1_LV is 1, as long as one of the PADs is at high-voltage level, it can trigger a wake-up. However, if RTC_CNTL_EXT_WAKEUP1_LV is 0, it needs all selected PADs to be

at low-voltage level to trigger a wake-up.

4 In Deep-sleep mode, only RTC GPIOs (not DIGITAL GPIOs) can work as wakeup source.

5 Wake-up is triggered by receiving any SDIO command.

6To wake up the chip with a Wi-Fi or BT source, the power mode switches between the Active, Modemand Light-sleep modes. The CPU, Wi-Fi, Bluetooth, and radio are woken up at predetermined intervals to keep Wi-Fi/BT connections active.

7Wake-up is triggered when the number or positive edges of RxD signal is greater than or equal to (UART_ACTIVE_THRESHOLD+2). Note that the RxD signal cannot be input through GPIO Matrix but only through IO_MUX.

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31 Low-Power Management (RTC_CNTL)

31.3.11 Reject Sleep

ESP32 implements a hardware mechanism that equips the chip with the ability to reject to sleep, which prevents the chip from going to sleep unexpectedly when some peripherals are still working but not detected by the CPU, thus guaranteeing the proper functioning of the peripherals.

All the wakeup sources specified in Table 31-2 (except UART) can also be configured as the causes to reject sleep.

Users can configure the reject to sleep option via the following registers.

•Configure the RTC_CNTL_SLP_REJECT field to enable or disable the option to reject to sleep:

–Set RTC_CNTL_LIGHT_SLP_REJECT_EN to enable reject-to-light-sleep.

–Set RTC_CNTL_DEEP_SLP_REJECT_EN to enable reject-to-deep-sleep.

•Read RTC_CNTL_REJECT_CAUSE to check the reason for rejecting to sleep.

31.3.12 RTC Timer

The RTC timer is a 48-bit counter that can be read. The clock is RTC_SLOW_CLK. Any reset/sleep mode, except for the power-up reset, will not stop or reset the RTC timer.

The RTC timer can be used to wake up the CPU at a designated time, and to wake up TOUCH or the ULP coprocessor periodically.

31.3.13 RTC Boot

Since the CPU, ROM and RAM are powered down during Deep-sleep and Hibernation mode, the wake-up time is much longer than that in Light sleep/Modem sleep, because of the ROM unpacking and data-copying from the flash (SPI booting). There are two types of SRAM in the RTC, named slow RTC memory and fast RTC memory, which remain powered-on in Deep-sleep mode. For small-scale codes (less than 8 KB), there are two methods of speeding up the wake-up time, i.e. avoiding ROM unpacking and SPI booting.

The first method is to use the RTC slow memory:

1.Set register RTC_CNTL_PROCPU_STAT_VECTOR_SEL for PRO_CPU (or register RTC_CNTL_APPCPU_STAT_VECTOR_ for APP_CPU) to 0.

2.Put the chip into sleep.

3.When the CPU is powered up, the reset vector starts from 0x50000000, instead of 0x40000400. ROM unpacking & SPI boot are not needed. The code in RTC memory has to do itself some initialization for the C program environment.

The second method is to use the fast RTC memory:

1.Set register RTC_CNTL_PROCPU_STAT_VECTOR_SEL for PRO_CPU (or register RTC_CNTL_APPCPU_STAT_VECTOR_ for APP_CPU) to 1.

2.Calculate CRC for the fast RTC memory, and save the result in register RTC_CNTL_RTC_STORE6_REG[31:0].

3.Input register RTC_CNTL_RTC_STORE7_REG[31:0] with the entry address in the fast RTC memory.

4.Put the chip into sleep.

5.When the CPU is powered up, after ROM unpacking and some necessary initialization, the CRC is calculated again. If the result matches with register RTC_CNTL_RTC_STORE6_REG[31:0], the CPU will jump to the

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