31 Low-Power Management (RTC_CNTL)

31 Low­Power Management (RTC_CNTL)

31.1Introduction

ESP32 offers efficient and flexible power-management technology to achieve the best balance between power consumption, wakeup latency and available wakeup sources. Users can select out of five predefined power modes of the main processors to suit specific needs of the application. In addition, to save power in powersensitive applications, control may be executed by the Ultra-Low-Power coprocessor (ULP coprocessor), while the main processors are in Deep-sleep mode.

31.2Features

•Five predefined power modes to support various applications

•Up to 16 KB of retention memory

•8 x 32 bits of retention registers

•ULP coprocessor enabled in all low-power modes

•RTC boot supported to shorten the wakeup latency

Figure 31­1. ESP32 Power Control

31.3Functional Description

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31 Low-Power Management (RTC_CNTL)

31.3.1 Overview

The low-power management unit includes voltage regulators, a power controller, power switch cells, power domain isolation cells, etc. Figure 31-1 shows the high-level architecture of ESP32’s low-power management.

31.3.2 Digital Core Voltage Regulator

The built-in voltage regulator can convert the external power supply (typically 3.3V) to 1.1V to support the internal digital core. It receives a wide range of external power supply from 1.8V to 3.6V, and provides an output voltage from 0.90V to 1.25V.

1.When XPD_DIG_REG == 1, the regulator outputs a 1.1V voltage and the digital core is able to run; when XPD_DIG_REG == 0, both the regulator and the digital core stop running.

2.DIG_REG_DBIAS[2:0] tunes the supply voltage of the digital core:

VDD_DIG = 0.90 + DBIAS · 0.05V

3. The current to the digital core comes from pin VDD3P3_CPU and pin VDD3P3_RTC.

Figure 31-2 shows the structure of a digital core’s voltage regulator.

Figure 31­2. Digital Core Voltage Regulator

31.3.3 Low­Power Voltage Regulator

The built-in low-power voltage regulator can convert the external power supply (typically 3.3V) to 1.1V to support the internal RTC core. To save power, it receives a wide range of external power supply from 1.8V to 3.6V, and supports an adjustable output voltage of 0.90V to 1.25V in normal work mode, a fixed output voltage of about 0.75V both in Deep-sleep mode and Hibernation mode.

1.When the pin CHIP_PU is at a high level, the low-power voltage regulator cannot be turned off. It should be switched only between normal-work mode and Deep-sleep mode.

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31Low-Power Management (RTC_CNTL)

2.In normal-work mode, RTC_DBIAS[2:0] can be used to tune the output voltage:

VDD_RTC = 0.90 + DBIAS · 0.05V

3.In Deep-sleep mode, the output voltage of the regulator is fixed at about 0.75V.

4.The current to the RTC core comes from pin VDD3P3_RTC.

Figure 31-3 shows the structure of a low-power voltage regulator.

Figure 31­3. Low­Power Voltage Regulator

31.3.4 Flash Voltage Regulator

The built-in flash voltage regulator can supply a voltage of 3.3V or 1.8V to other devices (flash, for example) in the system, with a maximum output current of 40 mA.

1.When XPD_SDIO_VREG == 1, the regulator outputs a voltage of 3.3V or 1.8V; when XPD_SDIO_VREG == 0, the output is high-impedance and, in this case, the voltage is provided by the external power supply.

2.When SDIO_TIEH == 1, the regulator shorts pin VDD_SDIO to pin VDD3P3_RTC. The regulator then outputs a voltage of 3.3V which is the voltage of pin VDD3P3_RTC. When SDIO_TIEH == 0, the inner loop ties the regulator output to the voltage of VREF, which is typically 1.8V.

3.DREFH_SDIO, DREFM_SDIO and DREFL_SDIO could be used to tune the reference voltage VREF slightly. However, it is recommended that users do not change the value of these registers, since it may affect the stability of the inner loop.

4.When the regulator output is 3.3V or 1.8V, the output current comes from the pin VDD3P3_RTC.

Figure 31-4 shows the structure of a flash voltage regulator.

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31 Low-Power Management (RTC_CNTL)

Figure 31­4. Flash Voltage Regulator

31.3.5 Brownout Detector

The brownout detector checks the voltage of pin VDD3P3_RTC. If the voltage drops rapidly and becomes too low, the detector would trigger a signal to shut down some power-consuming blocks (such as LNA, PA, etc.) to allow extra time for the digital block to save and transfer important data. The power consumption of the detector is ultra low. It remains enabled whenever the chip is powered on, with an adjustable trigger level calibrated around 2.5V.

1.As the output of the brownout detector, RTC_CNTL_BROWN_OUT_DET goes high when the voltage of pin VDD3P3_RTC is lower than the threshold value.

2.RTC_CNTL_DBROWN_OUT_THRES[2:0] is used to tune the threshold voltage, which is usually calibrated around 2.5V.

Figure 31-5 shows the structure of a brownout detector.

Figure 31­5. Brownout Detector

31.3.6 RTC Module

The RTC module is designed to handle the entry into, and exit from, the low-power mode, and control the clock sources, PLL, power switch and isolation cells to generate power-gating, clock-gating, and reset signals. As for the low-power management, RTC is composed of the following modules (see Figure 31-6):

• RTC main state machine: records the power state.

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31Low-Power Management (RTC_CNTL)

•Digital & analog power controller: generates actual power-gating/clock-gating signals for digital parts and analog parts.

•Sleep & wakeup controller: handles the entry into & exit from the low-power mode.

•Timers: include RTC main timer, ULP coprocessor timer and touch timer.

•Low-Power processor and sensor controllers: include ULP coprocessor, touch controller, SAR ADC controller, etc.

•Retention memory:

–RTC slow memory: an 8 KB SRAM, mostly used as retention memory or instruction & data memory for the ULP coprocessor. The CPU accesses it through the APB, starting from address 0x50000000.

–RTC fast memory: an 8 KB SRAM, mostly used as retention memory. The CPU accesses it through IRAM0/DRAM0. Fast RTC memory is about 10 times faster than the RTC slow memory.

•Retention registers: always-on registers of 8 x 32 bits, serving as data storage.

•RTC IO pads: 18 always-on analog pads, usually functioning as wake-up sources.

Figure 31­6. RTC Structure

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31 Low-Power Management (RTC_CNTL)

31.3.7 Low­Power Clocks

In the low-power mode, the 40 MHz crystal and PLL are usually powered down to save power. But clocks are needed for the chip to remain active in the low-power mode.

For the RTC core, there are five possible clock sources:

•external low-speed (32.768 kHz) crystal clock XTL32K_CLK,

•external high-speed (2 MHz ~ 40 MHz) crystal clock XTAL_DIV_CLK,

•internal RC oscillator RC_SLOW_CLK (typically about 150 kHz and adjustable),

•internal 8-MHz oscillator RC_FAST_CLK, and

•internal 31.25-kHz clock RC_FAST_DIV_CLK (derived from the internal 8-MHz oscillator divided by 256).

RTC Clock

Figure 31­7. RTC Low­Power Clocks

For the digital core, LOW_POWERE_CLK is switched among four sources. For details, please see Figure 31- 8.

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Figure 31­8. Digital Low­Power Clocks

Low-power Clock

31.3.8 Power­Gating Implementation

Figure 31­9. RTC States

The switch among power-gating states can be see in Figure 31-9. The actual power-control signals could also be set by software as force-power-up (FPU) or force-power-down (FPD). Since the power domains can be powergated independently, there are many combinations for different applications. Table 31-1 shows how the power domains in ESP32 are controlled.

Table 31­1. RTC Power Domains

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