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30ULP Coprocessor (ULP)

1.Master generates a START condition.

2.Master sends slave address, with r/w bit set to 0 (“write”). Slave address is obtained from SENS_I2C_SLAVE_ADDRn, where n is given as an argument to the I2C_WR instruction.

3.Slave generates ACK.

4.Master sends slave register address (given as an argument to the I2C_WR instruction).

5.Slave generates ACK.

6.Master generates a repeated START condition.

7.Master sends slave address, with r/w bit set to 0 (“write”).

8.Master sends one byte of data.

9.Slave generates ACK.

10.Master generates a STOP condition.

 

1

2

3

4

5

6

7

8

Master

 

START

 

Slave Address W

 

Reg Address

 

RSTRT

 

Slave Address W

 

Data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slave

 

 

 

 

ACK

 

ACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 30­22. I²C Write Operation

 

 

9 10

STOP

ACK

30.6.2.3 Detecting Error Conditions

ULP I2C_RD and I2C_WR instructions will not report error conditions, such as a NACK from a slave, via ULP registers. Instead, applications can query specific bits in the RTC_I2C_INT_ST_REG register to determine if the transaction was successful. To enable checking for specific communication events, their corresponding bits should be set in register RTC_I2C_INT_EN_REG. Note that the bit map is shifted by 1. If a specific communication event is detected and set in register RTC_I2C_INT_ST_REG, it can then be cleared using RTC_I2C_INT_CLR_REG.

30.6.2.4 Connecting I²C Signals

SDA and SCL signals can be mapped onto two out of the four GPIO pins, which are identified in Table RTC_MUX Pin Summary in Chapter IO_MUX and GPIO Matrix, using the RTCIO_SAR_I2C_IO_REG register.

30.7Register Summary

30.7.1 SENS_ULP Address Space

Name

Description

 

Address

Access

ULP Timer cycles select

 

 

 

 

 

 

 

 

 

SENS_ULP_CP_SLEEP_CYC0_REG

Timer cycles setting 0

 

0x3FF48818

R/W

 

 

 

 

 

SENS_ULP_CP_SLEEP_CYC1_REG

Timer cycles setting 1

 

0x3FF4881C

R/W

 

 

 

 

 

SENS_ULP_CP_SLEEP_CYC2_REG

Timer cycles setting 2

 

0x3FF48820

R/W

 

 

 

 

 

SENS_ULP_CP_SLEEP_CYC3_REG

Timer cycles setting 3

 

0x3FF48824

R/W

 

 

 

 

 

SENS_ULP_CP_SLEEP_CYC4_REG

Timer cycles setting 4

 

0x3FF48828

R/W

 

 

 

 

 

Espressif Systems

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ESP32 TRM (Version 5.0)

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30 ULP Coprocessor (ULP)

RTC I2C slave address select

SENS_SAR_SLAVE_ADDR1_REG

I²C addresses 0 and 1

0x3FF4883C

R/W

 

 

 

 

SENS_SAR_SLAVE_ADDR2_REG

I²C addresses 2 and 3

0x3FF48840

R/W

 

 

 

 

SENS_SAR_SLAVE_ADDR3_REG

I²C addresses 4 and 5

0x3FF48844

R/W

 

 

 

 

SENS_SAR_SLAVE_ADDR4_REG

I²C addresses 6 and 7, I2C control

0x3FF48848

R/W

 

 

 

 

RTC I²C control

 

 

 

 

 

 

 

SENS_SAR_I2C_CTRL_REG

I²C control registers

0x3FF48850

R/W

 

 

 

 

30.7.2 RTC_I2C Address Space

Name

Description

Address

Access

RTC I²C control registers

 

 

 

 

 

 

 

RTC_I2C_CTRL_REG

Transmission setting

0x3FF48C04

R/W

 

 

 

 

RTC_I2C_DEBUG_STATUS_REG

Debug status

0x3FF48C08

R/W

 

 

 

 

RTC_I2C_TIMEOUT_REG

Timeout setting

0x3FF48C0C

R/W

 

 

 

 

RTC_I2C_SLAVE_ADDR_REG

Local slave address setting

0x3FF48C10

R/W

 

 

 

 

RTC I2C signal setting registers

 

 

 

 

 

 

 

RTC_I2C_SDA_DUTY_REG

Configures the SDA hold time after a nega-

0x3FF48C30

R/W

tive SCL edge

 

 

 

 

 

 

 

RTC_I2C_SCL_LOW_PERIOD_REG

Configures the low level width of SCL

0x3FF48C00

R/W

 

 

 

 

RTC_I2C_SCL_HIGH_PERIOD_REG

Configures the high level width of SCL

0x3FF48C38

R/W

 

 

 

 

RTC_I2C_SCL_START_PERIOD_REG

Configures the delay between the SDA and

0x3FF48C40

R/W

SCL negative edge for a start condition

 

 

 

 

 

 

 

RTC_I2C_SCL_STOP_PERIOD_REG

Configures the delay between the SDA and

0x3FF48C44

R/W

SCL positive edge for a stop condition

 

 

 

 

 

 

 

RTC I²C interrupt registers ­ listed only for debugging

 

 

 

 

 

 

RTC_I2C_INT_CLR_REG

Clear status of I²C communication events

0x3FF48C24

R/W

 

 

 

 

RTC_I2C_INT_EN_REG

Enable capture of I²C communication status

0x3FF48C28

R/W

events

 

 

 

 

 

 

 

RTC_I2C_INT_ST_REG

Status of captured I²C communication

0x3FF48C2C

R/O

events

 

 

 

 

 

 

 

Note:

 

 

 

Interrupts from RTC_I2C are not connected. The interrupt registers above are listed only for debugging

 

purposes.

 

 

 

Espressif Systems

671

ESP32 TRM (Version 5.0)

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