
- •NI 5102 User Manual
- •Worldwide Technical Support and Product Information
- •National Instruments Corporate Headquarters
- •Worldwide Offices
- •Important Information
- •Warranty
- •Copyright
- •Trademarks
- •WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS
- •Contents
- •About This Manual
- •Conventions Used in This Manual
- •Related Documentation
- •About Your NI 5102
- •Acquiring Data with Your NI 5102
- •Interactively Controlling your NI 5102 with the Scope Soft Front Panel
- •NI-SCOPE Driver
- •NI Application Software
- •Using PXI with CompactPCI
- •Table 1-1. NI 5102 (PXI) J2 Pin Assignment
- •Optional Equipment
- •What You Need to Get Started
- •Unpacking
- •Installing the NI 5102
- •Table 2-1. NI 5102 (USB) LED Patterns
- •Hardware Configuration
- •Understanding Digitizers
- •Nyquist Theorem
- •Figure 3-1. Aliased Sine Wave When Waveform is Under Sampled
- •Analog Bandwidth
- •Figure 3-2. Analog Bandwidth
- •Sample Rate
- •Figure 3-3. 1 MHz Sine Wave Sample
- •Vertical Sensitivity
- •Figure 3-4. Transfer Function of a 3-Bit ADC
- •ADC Resolution
- •Record Length
- •Triggering Options
- •Making Accurate Measurements
- •Figure 3-5. Dynamic Range of an 8-Bit ADC with Three Different Gain Settings
- •Passive Probe
- •How to Compensate Your Probe
- •Figure 3-7. Connecting the Probe Compensation Cabling
- •Figure 3-8. Probe Compensation Comparison
- •Active and Current Probes
- •Figure 4-1. NI 5102 (PCI, PXI, ISA) Block Diagram
- •Figure 4-2. NI 5102 (PCMCIA, USB) Block Diagram
- •I/O Connector
- •Figure 4-3. NI 5102 (PCI, ISA) I/O Connectors
- •Figure 4-4. NI 5102 (PCMCIA) I/O Connectors
- •Figure 4-6. NI 5102 (PXI) I/O Connectors
- •Signal Connections
- •Table 4-1. I/O Connector Signal Descriptions
- •Serial Communications Port (AUX)
- •Analog Input
- •Table 4-3. AC/DC Coupling Change Settling Rates with NI Probes
- •ADC Pipeline Delay
- •Figure 4-7. Scan Clock Delay
- •Acquisition Modes
- •Posttrigger Acquisition
- •Table 4-4. Possible Number of Samples for Posttriggered Scans
- •Figure 4-8. Posttrigger Acquisition
- •Table 4-5. Posttrigger Acquisition Signals
- •Pretrigger Acquisition
- •Table 4-6. Possible Number of Samples for Pretriggered Mode
- •Figure 4-9. Pretrigger Acquisition
- •Table 4-7. Pretrigger Acquisition Signals
- •Trigger Sources
- •Figure 4-10. Scan Clock, Start Trigger, and Stop Trigger Signal Sources
- •Analog Trigger Circuit
- •Trigger Hold-off
- •Figure 4-11. Pretrigger and Posttrigger Acquisitions with Hold-off
- •Random Interleaved Sampling
- •Calibration
- •RTSI Bus Trigger and Clock Lines
- •Figure 4-12. RTSI Bus Trigger Lines
- •PFI Lines
- •PFI Lines as Inputs
- •PFI Lines as Outputs
- •Master/Slave Operation
- •Restrictions
- •Connecting Devices
- •Glossary
- •Numbers/Symbols
- •Index

Chapter 4 Hardware Overview
your NI 5102 and afterwards whenever operating environment conditions change.
Externally recalibrate the NI 5102 when its interval has expired. This requires connecting a precision reference to your device, and is normally performed at NI or a metrology lab. See Appendix A, Specifications, for more information about calibration intervals, and your NI 5102 Calibration Procedure for detailed external calibration instructions. This procedure is available at C:\VXIpnp\Win95\NISCOPE\Documents\ ni5102cal.pdf.
You may choose to write your own external calibration procedure in NI-SCOPE. Refer to your NI-SCOPE Software User Manual for more information about calibration.
RTSI Bus Trigger and Clock Lines
♦NI 5102 (PCI and ISA)
The RTSI bus (not available on the NI 5102 PCMCIA or USB) allows NI digitizers to synchronize timing and triggering on multiple devices. The RTSI bus has seven bidirectional trigger lines and one bidirectional clock signal.
You can program any of the seven trigger lines as inputs to provide
Start Trigger, Stop Trigger, Sample Clock and Board Clock signals sourced from a master device. Similarly, you can program a master NI 5102 to output its internal Start Trigger, Stop Trigger, Scan Clock, and Analog Trigger Circuit Output signals on any of the trigger lines, as shown in Figure 4-12.
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Chapter 4 Hardware Overview
Analog Trigger Circuit Output
RTSI In <0..6>
Software
PFI1, PFI2
Analog Trigger Circuit Output
RTSI In <0..6>
PFI1, PFI2
RTSI In <0..6>
Internal Scan
PFI1, PFI2
Analog Trigger Circuit Output
CH0
CH1
TRIG
RTSI Trigger 0
RTSI Trigger 1
RTSI Trigger 6
Start
7 Trigger
Selection
2
Stop
7 Trigger
Selection
2
7Scan Clock
2 Selection
Analog
Trigger
Circuit
RTSI In 0
RTSI In 1
Start Trigger
Stop Trigger
Scan Clock
Analog Trigger
Circuit Output
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Mux |
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Scan Clock |
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Circuit Output |
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Start Trigger |
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Stop Trigger |
Digital |
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Scan Clock |
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Figure 4-12. RTSI Bus Trigger Lines
The RTSI bus clock line is a special clock line on the RTSI bus that can only carry the timebase of the master to the slaves. For the smallest jitter between measurements on different devices, you should configure the slaves to use the RTSI bus clock from the master NI 5102.
♦NI 5102 (PXI)
The NI 5102 (PXI) uses the PXI Trigger <0..5> to carry RTSI Trigger <0..5> and uses PXI Trigger 7 to carry the RTSI clock signal to all other PXI slots in the system. RTSI Trigger 6 is reserved for use with PXI Star Trigger, which the NI 5102 can receive but may not drive.
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