- •1 General description
- •2 Features
- •3 Ordering information
- •4 Marking
- •5 Functional diagram
- •6 Pinning information
- •6.1 Pinning
- •6.2 Pin description
- •7 Functional description
- •8 Limiting values
- •9 Recommended operating conditions
- •10 Static characteristics
- •11 Dynamic characteristics
- •11.1 Waveform and test circuit
- •12 Package outline
- •13 Abbreviations
- •14 Revision history
- •15 Legal information
- •Contents
Nexperia |
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74HC1G08; 74HCT1G08 |
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2-input AND gate |
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4 |
Marking |
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Table 2. Marking codes |
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Type number |
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Marking |
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74HC1G08GW |
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HE |
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74HCT1G08GW |
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TE |
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74HC1G08GV |
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H08 |
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74HCT1G08GV |
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T08 |
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5 |
Functional diagram |
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1 |
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1 |
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B |
Y |
4 |
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& |
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4 |
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2 |
A |
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2 |
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mna113 |
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mna114 |
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Figure 1. Logic symbol |
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Figure 2. IEC logic symbol |
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B |
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Y |
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A |
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mna115 |
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Figure 3. Logic diagram
6Pinning information
6.1Pinning
74HC1G08
74HCT1G08
B |
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VCC |
1 |
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5 |
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A |
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2 |
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GND |
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Y |
3 |
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4 |
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001aaf102 |
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Figure 4. Pin configuration
74HC_HCT1G08 |
All information provided in this document is subject to legal disclaimers. |
© Nexperia B.V. 2018. All rights reserved. |
Product data sheet |
Rev. 5 — 14 March 2018 |
2 / 12 |
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