STM32F105xx, STM32F107xx |
Application block diagrams |
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Appendix A Application block diagrams
A.1 USB OTG FS interface solutions
Figure 46. USB OTG FS device mode
STM32F105xx/STM32F107xx |
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OTG PHY |
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USB |
DP |
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Full-speed |
DM |
connector |
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transceiver |
To host |
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DP |
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USB |
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DM |
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OTG |
HNP |
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-B |
VBUS |
Full-speed |
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VBUS |
USB Micro |
VSS |
core |
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ID |
VSS |
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SRP |
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VDD |
5 V to VDD |
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Regulator(1) |
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ai15653b |
1. Use a regulator if you want to build a bus-powered device.
DocID15274 Rev 7 |
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Application block diagrams |
STM32F105xx, STM32F107xx |
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Figure 47. Host connection
STM32F105xx/STM32F107xx |
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OTG PHY |
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USB |
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DP |
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full-speed/ |
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DM |
A connector |
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low-speed |
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transceiver |
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USB |
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OTG |
HNP |
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Full-speed |
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VBUS |
td- |
core |
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S |
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USB |
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ID |
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VSS |
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(2) |
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SRP |
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VDD |
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EN |
Current-limited |
5 V |
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GPIO |
power distribution |
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GPIO + IRQ |
OVRCR |
switch |
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flag |
STMPS2141STR(1) |
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ai15654b |
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1. STMPS2141STR needed only if the application has to support bus-powered devices.
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DocID15274 Rev 7 |
STM32F105xx, STM32F107xx |
Application block diagrams |
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Figure 48. OTG connection (any protocol)
STM32F105xx/STM32F107xx |
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OTG PHY |
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USB |
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DP |
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full-speed/ |
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DM |
connector |
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low-speed |
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transceiver |
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ID |
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USB |
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-AB |
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OTG |
HNP |
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VBUS |
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Full-speed |
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Micro |
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core |
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ID |
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VSS |
USB |
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SRP |
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VDD |
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EN |
Current-limited |
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GPIO |
power distribution 5 V |
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GPIO + IRQ |
OVRCR |
switch |
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flag |
STMPS2141STR(1) |
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ai15655b |
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1. STMPS2141STR needed only if the application has to support bus-powered devices.
A.2 Ethernet interface solutions
Figure 49. MII mode using a 25 MHz crystal
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STM32F107xx |
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MCU |
Ethernet |
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MII_TX_CLK |
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MII_TX_EN |
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MAC 10/100 |
MII_TXD[3:0] |
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MII_CRS |
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MII_COL |
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HCLK(1) |
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MII_RX_CLK |
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MII_RXD[3:0] |
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IEEE1588 PTP |
MII_RX_DV |
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Timer |
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MII_RX_ER |
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input |
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TIM2 |
trigger Timestamp |
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MDIO |
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comparator |
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MDC |
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PPS_OUT(2) |
XTAL |
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PLL |
HCLK |
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25 MHz |
OSC |
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PHY_CLK 25 MHz |
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Ethernet
PHY 10/100
MII
= 15 pins
MII + MDC = 17 pins
XT1
ai15656
1.HCLK must be greater than 25 MHz.
2.Pulse per second when using IEEE1588 PTP, optional signal.
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Application block diagrams |
STM32F105xx, STM32F107xx |
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Figure 50. RMII with a 50 MHz oscillator
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STM32F107xx |
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Ethernet |
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MCU |
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PHY 10/100 |
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Ethernet |
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RMII_TX_EN |
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RMII_TXD[1:0] |
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MAC 10/100 |
RMII |
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HCLK(1) |
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RMII_RXD[1:0] |
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RMII_CRX_DV |
= 7 pins |
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RMII + MDC |
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RMII_REF_CLK |
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IEEE1588 PTP |
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= 9 pins |
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Timer |
MDIO |
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input |
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MDC |
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TIM2 |
trigger |
Timestamp |
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comparator |
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/2 or /20 |
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2.5 or 25 MHz synchronous |
50 MHz |
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OSC |
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PLL |
HCLK |
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50 MHz |
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PHY_CLK |
50 MHz |
XT1 |
50 MHz |
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ai15657 |
1. HCLK must be greater than 25 MHz.
Figure 51. RMII with a 25 MHz crystal and PHY with PLL
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STM32F107xx |
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Ethernet |
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PHY 10/100 |
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MCU |
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RMII_TX_EN |
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Ethernet |
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RMII_TXD[1:0] |
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MAC 10/100 |
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HCLK(1) |
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RMII_RXD[1:0] |
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RMII |
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RMII_CRX_DV |
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= 7 pins |
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RMII_REF_CLK |
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REF_CLK RMII + MDC |
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Timer |
IEEE1588 PTP |
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MDIO |
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= 9 pins |
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input |
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MDC |
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TIM2 |
trigger |
Timestamp |
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comparator |
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2.5 or 25 MHz |
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/2 or /20 |
50 MHz |
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synchronous |
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XTAL |
OSC |
PLL |
HCLK |
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PLL |
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25 MHz |
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PHY_CLK |
25 MHz |
XT1 |
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ai15658
1. HCLK must be greater than 25 MHz.
94/104 |
DocID15274 Rev 7 |
STM32F105xx, STM32F107xx |
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Application block diagrams |
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Figure 52. RMII with a 25 MHz crystal |
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STM32F107xx |
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Ethernet |
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PHY 10/100 |
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MCU |
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RMII_TX_EN |
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Ethernet |
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RMII_TXD[1:0] |
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MAC 10/100 |
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HCLK |
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RMII_RXD[1:0] |
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RMII |
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RMII_CRX_DV |
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50 MHz |
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RMII_REF_CLK |
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50 MHz |
RMII + MDC |
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IEEE1588 PTP |
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= 9 pins |
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Timer |
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MDIO |
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input |
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MDC |
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TIM2 |
trigger |
Time stamp |
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comparator |
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XTAL |
OSC |
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50 MHz |
25 MHz |
PLLS |
XT1/XT2 |
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NS DP83848(1) |
ai15659b
1.The NS DP83848 is recommended as the input jitter requirement of this PHY. It is compliant with the output jitter specification of the MCU.
DocID15274 Rev 7 |
95/104 |