STM32F105xx, STM32F107xx

Electrical characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Comments

VDDA

Analog supply voltage

2.4

-

3.6

V

-

VREF+

Reference supply voltage

2.4

-

3.6

V

VREF+ must always be below VDDA

VSSA

Ground

0

-

0

V

-

R

(1)

Resistive load with buffer ON

5

-

-

kΩ

-

LOAD

Impedance output with buffer

When the buffer is OFF, the

R

O

(1)

-

-

15

kΩ

Minimum resistive load between

OFF

DAC_OUT and VSS to have a 1%

accuracy is 1.5 MΩ

C

(1)

Maximum capacitive load at

Capacitive load

-

-

50

pF

DAC_OUT pin (when the buffer is

LOAD

ON).

DAC_OUT

Lower DAC_OUT voltage

It gives the maximum output

0.2

-

-

V

excursion of the DAC.

min(1)

with buffer ON

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at VREF+ =

DAC_OUT

Higher DAC_OUT voltage

-

-

VDDA – 0.2

V

3.6 V and (0x155) to (0xEAB) at

(1)

with buffer ON

max

VREF+ = 2.4 V

DAC_OUT

Lower DAC_OUT voltage

-

0.5

-

mV

min(1)

with buffer OFF

It gives the maximum output

DAC_OUT

Higher DAC_OUT voltage

-

-

VREF+ – 1LSB

V

excursion of the DAC.

(1)

with buffer OFF

max

DAC DC current

With no load, worst code (0xF1C)

IDDVREF+

consumption in quiescent

-

-

220

µA

at VREF+ = 3.6 V in terms of DC

mode (Standby mode)

consumption on the inputs

-

-

380

µA

With no load, middle code (0x800)

DAC DC current

on the inputs

IDDA

consumption in quiescent

With no load, worst code (0xF1C)

mode (Standby mode)

-

-

480

µA

at VREF+ = 3.6 V in terms of DC

consumption on the inputs

Differential non linearity

-

-

±0.5

LSB

Given for the DAC in 10-bit

DNL(2)

configuration.

Difference between two

consecutive code-1LSB)

-

-

±2

LSB

Given for the DAC in 12-bit

configuration.

Integral non linearity

-

-

±1

LSB

Given for the DAC in 10-bit

(difference between

configuration.

INL(2)

measured value at Code i

and the value at Code i on a

Given for the DAC in 12-bit

-

-

±4

LSB

line drawn between Code 0

and last Code 1023)

configuration.

DocID15274 Rev 7

79/104

Electrical characteristics

STM32F105xx, STM32F107xx

Table 56. DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max

Unit

Comments

Offset error

-

-

±10

mV

Given for the DAC in 12-bit

configuration

(difference between

Offset(2)

-

-

±3

LSB

Given for the DAC in 10-bit at

measured value at Code

VREF+ = 3.6 V

(0x800) and the ideal value =

Given for the DAC in 12-bit at

VREF+/2)

-

-

±12

LSB

VREF+ = 3.6 V

Gain

Gain error

-

-

±0.5

%

Given for the DAC in 12bit

error(2)

configuration

Settling time (full scale: for a

10-bit input code transition

CLOAD ≤ 50 pF,

tSETTLING

(2)

between the lowest and the

-

3

4

µs

highest input codes when

RLOAD ≥ 5 kΩ

DAC_OUT reaches final

value ±1LSB

Update

Max frequency for a correct

≤ 50 pF,

DAC_OUT change when

C

rate(2)

small variation in the input

-

-

1

MS/s

RLOADLOAD

≥ 5 kΩ

code (from code i to i+1LSB)

(2)

Wakeup time from off state

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

t

WAKEUP

(Setting the ENx bit in the

-

6.5

10

µs

input code between lowest and

DAC Control register)

highest possible ones.

PSRR+ (1)

Power supply rejection ratio

(to V

DDA

) (static DC

-

–67

–40

dB

No R

, C

LOAD

= 50 pF

LOAD

measurement

Buffer(1)

R LOAD

12-bit

DACx_OUT

digital to

analog

converter

C LOAD

80/104

DocID15274 Rev 7

STM32F105xx, STM32F107xx

Electrical characteristics

Symbol

Parameter

Min

Typ

Max

Unit

(1)

V

SENSE

linearity with temperature

-

±

±

°C

TL

1

2

Avg_Slope(1)

Average slope

4.0

4.3

4.6

mV/°C

V (1)

Voltage at 25 °C

1.34

1.43

1.52

V

25

tSTART(2)

Startup time

4

-

10

µs

TS_temp(3)(2)

ADC sampling time when reading the

-

-

17.1

µs

temperature

DocID15274 Rev 7

81/104