TPS767D301-EP
www.ti.com |
SGLS327A –FEBRUARY 2006 –REVISED APRIL 2010 |
DUAL-OUTPUT LOW-DROPOUT LINEAR REGULATOR
Check for Samples: TPS767D301-EP
FEATURES
•Controlled Baseline
–One Assembly/Test Site, One Fabrication Site
•Extended Temperature Performance of –55°C to 125°C
•Enhanced Diminishing Manufacturing Sources (DMS) Support
•Enhanced Product-Change Notification
•Qualification Pedigree
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified
performance and environmental limits.
•Dual Output Voltages for Split-Supply Applications
•Output Current Range of 0 mA to 1.0 A Per Regulator
•3.3-V/Adjustable Output
•Fast Transient Response
•3% Tolerance Over Load and Temperature
•Dropout Voltage Typically 350 mV at 1 A
•Ultra-Low 85-mA Typical Quiescent Current
•1-mA Quiescent Current During Shutdown
•Dual Open-Drain Power-On Reset With 200-ms Delay for Each Regulator
• 28-Pin PowerPAD™ TSSOP Package
•Thermal Shutdown Protection for Each Regulator
PWP PACKAGE
(TOP VIEW)
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1 |
28 |
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NC |
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1RESET |
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NC |
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2 |
27 |
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NC |
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1GND |
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3 |
26 |
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NC |
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4 |
25 |
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1FB/NC |
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1EN |
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1IN |
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5 |
24 |
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1OUT |
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1IN |
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6 |
23 |
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1OUT |
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NC |
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7 |
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2RESET |
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NC |
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8 |
21 |
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NC |
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2GND |
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9 |
20 |
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NC |
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10 |
19 |
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NC |
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2EN |
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2IN |
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11 |
18 |
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2OUT |
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2IN |
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12 |
17 |
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2OUT |
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NC |
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13 |
16 |
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NC |
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NC |
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14 |
15 |
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NC |
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NC − No internal connection
DESCRIPTION/ORDERING INFORMATION
The TPS767D301-EP dual-voltage regulator offers fast transient response, low dropout (LDO) voltages, and dual outputs in a compact package and incorporates stability with 10-mF low-ESR output capacitors.
The TPS767D301-EP dual-voltage regulator is designed primarily for DSP applications. This device can be used in any mixed-output voltage application, with each regulator supporting up to 1 A. Dual active-low reset (RESET) signals allow resetting of core logic and I/O separately.
Table 1. ORDERING INFORMATION
TJ |
REGULATOR 1 |
REGULATOR 2 |
TSSOP (PWP) |
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VO |
VO |
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–55°C to 125°C |
Adjustable (1.5 V to 5.5 V) |
3.3 V |
TPS767D301MPWPREP |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. |
Copyright © 2006–2010, Texas Instruments Incorporated |
Products conform to specifications per the terms of the Texas |
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Instruments standard warranty. Production processing does not |
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necessarily include testing of all parameters. |
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TPS767D301-EP
SGLS327A –FEBRUARY 2006–REVISED APRIL 2010 www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
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DROPOUT VOLTAGE |
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vs |
LOAD TRANSIENT RESPONSE |
FREE-AIR TEMPERATURE |
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100 |
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in |
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mV |
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VO = 3.3 V |
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50 |
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CL =100 F |
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− Change |
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Voltage − |
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TA = 25°C |
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0 |
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O |
Output |
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V |
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−50 |
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A |
−100 |
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− |
1 |
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Current |
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0.5 |
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− Output |
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0 |
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O |
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I |
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0 |
20 |
40 |
60 |
80 |
100 |
120 |
140 |
160 |
180 |
200 |
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t − T ime − s |
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103 |
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IO = 1 A |
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102 |
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− mV |
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V oltage |
101 |
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− Dropout |
100 |
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IO = 10 mA |
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DO |
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V |
10−1 |
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VO = 3.3 V |
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I |
= 0 |
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CO = 10 F |
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O |
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10−2 |
−40 |
−20 |
0 |
20 |
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60 |
80 |
100 |
120 |
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−60 |
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TA − Free-Air T emperature − °C |
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Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 85 mA over the full range of output current, 0 mA to 1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO device also features a sleep mode; applying a TTL high signal to enable (EN) shuts down the regulator, reducing the quiescent current to 1 mA at TJ = 25°C.
The RESET output of the TPS767D301-EP initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS767D301-EP monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
The TPS767D301-EP is offered in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 3% over line, load, and temperature ranges. The TPS767D301-EP is available in a 28-pin PWP (TSSOP) package. The device operates over a junction temperature range of –55°C to 125°C.
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TPS767D3xx |
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VI |
5 |
RESET |
28 |
RESET |
IN |
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6 |
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250 kΩ |
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IN |
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24 |
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OUT |
VO |
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C1 |
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4 |
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23 |
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0.1 μF |
OUT |
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EN |
+ |
CO |
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50 V |
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10 μF |
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GND |
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3 |
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Figure 1. Typical Application Circuit (Fixed Versions) for Single Channel
2 |
Submit Documentation Feedback |
Copyright © 2006–2010, Texas Instruments Incorporated |
Product Folder Link(s): TPS767D301-EP
TPS767D301-EP
www.ti.com |
SGLS327A –FEBRUARY 2006 –REVISED APRIL 2010 |
FUNCTIONAL BLOCK DIAGRAM
Adjustable Version (for Each LDO)
IN |
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EN |
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RESET |
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_ |
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+ |
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OUT |
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+ |
200-ms Delay |
R1 |
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Vref = 1.1834 V |
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R2 |
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GND |
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FUNCTIONAL BLOCK DIAGRAM
Fixed-Voltage Version (for Each LDO)
IN |
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EN |
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RESET |
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+ |
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OUT |
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+ |
200-ms Delay |
R1 |
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Vref = 1.1834 V |
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FB/NC |
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R2 |
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GND |
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External to the device
Copyright © 2006–2010, Texas Instruments Incorporated |
Submit Documentation Feedback |
3 |
Product Folder Link(s): TPS767D301-EP
TPS767D301-EP
SGLS327A –FEBRUARY 2006–REVISED APRIL 2010 www.ti.com
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TERMINAL FUNCTIONS |
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TERMINAL |
I/O |
DESCRIPTION |
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NAME |
NO. |
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1GND |
3 |
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Regulator 1 ground |
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4 |
I |
Regulator 1 enable |
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1EN |
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1IN |
5, 6 |
I |
Regulator 1 input supply voltage |
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2GND |
9 |
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Regulator 2 ground |
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10 |
I |
Regulator 2 enable |
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2EN |
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2IN |
11, 12 |
I |
Regulator 2 input supply voltage |
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2OUT |
17, 18 |
O |
Regulator 2 output voltage |
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22 |
O |
Regulator 2 reset |
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2RESET |
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1OUT |
23, 24 |
O |
Regulator 1 output voltage |
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1FB/NC |
25 |
I |
Regulator 1 output voltage feedback for adjustable version and no connect for fixed-output |
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version |
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28 |
O |
Regulator 1 reset |
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1RESET |
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NC |
1, 2, 7, 8, 13–16, |
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No connection |
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19–21, 26, 27 |
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TIMING DIAGRAM
VI |
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Vres |
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Vres |
See Note A. |
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t |
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VO |
VIT + |
VIT + |
See Note B. |
See Note B. |
Threshold |
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Voltage |
Less than 5% of the |
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VIT − |
output voltage |
VIT − |
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t |
RESET |
200-ms |
200-ms |
Output |
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Delay |
Delay |
Output |
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Output |
Undefined |
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Undefined |
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t |
A.Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology.
B.VIT – Trip voltage typically is 5% lower than the output voltage (95% VO).
4 |
Submit Documentation Feedback |
Copyright © 2006–2010, Texas Instruments Incorporated |
Product Folder Link(s): TPS767D301-EP