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17.11.36 TIMSK5 – Timer/Counter 5 Interrupt Mask Register

Bit

7

6

5

4

3

2

1

0

 

(0x73)

 

ICIE5

OCIE5C

OCIE5B

OCIE5A

TOIE5

TIMSK5

Read/Write

 

R

R

R/W

R

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 101) is executed when the ICFn Flag, located in TIFRn, is set.

• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 101) is executed when the OCFnC Flag, located in TIFRn, is set.

• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 101) is executed when the OCFnB Flag, located in TIFRn, is set.

• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 101) is executed when the OCFnA Flag, located in TIFRn, is set.

• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 101) is executed when the TOVn Flag, located in TIFRn, is set.

17.11.37 TIFR1 – Timer/Counter1 Interrupt Flag Register

Bit

7

6

5

4

3

2

1

0

 

0x16 (0x36)

 

ICF1

OCF1C

OCF1B

OCF1A

TOV1

TIFR1

Read/Write

 

R

R

R/W

R

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

17.11.38 TIFR3 – Timer/Counter3 Interrupt Flag Register

Bit

7

6

5

4

3

2

1

0

 

0x18 (0x38)

 

ICF3

OCF3C

OCF3B

OCF3A

TOV3

TIFR3

Read/Write

 

R

R

R/W

R

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

17.11.39 TIFR4 – Timer/Counter4 Interrupt Flag Register

Bit

7

6

5

4

3

2

1

0

 

0x19 (0x39)

 

ICF4

OCF4C

OCF4B

OCF4A

TOV4

TIFR4

Read/Write

 

R

R

R/W

R

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

162

2549Q–AVR–02/2014

17.11.40 TIFR5 – Timer/Counter5 Interrupt Flag Register

Bit

7

6

5

4

3

2

1

0

 

0x1A (0x3A)

 

ICF5

OCF5C

OCF5B

OCF5A

TOV5

TIFR5

Read/Write

 

R

R

R/W

R

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

• Bit 5 – ICFn: Timer/Countern, Input Capture Flag

This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register (ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the counter reaches the TOP value.

ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICFn can be cleared by writing a logic one to its bit location.

• Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register C (OCRnC).

Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.

OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is executed. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.

• Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB).

Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag.

OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.

• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn value matches the Output Compare Register A (OCRnA).

Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA Flag.

OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCFnA can be cleared by writing a logic one to its bit location.

• Bit 0 – TOVn: Timer/Countern, Overflow Flag

The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOVn Flag is set when the timer overflows. Refer to Table 17-2 on page 145 for the TOVn Flag behavior when using another WGMn3:0 bit setting.

TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed. Alternatively, TOVn can be cleared by writing a logic one to its bit location.

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

163

2549Q–AVR–02/2014