13.3.11Alternate Functions of Port L
The Port L alternate pin configuration is as follows:
Table 13-33. Port L Pins Alternate Functions
Port Pin |
Alternate Function |
|
|
PL7 |
– |
|
|
PL6 |
– |
|
|
PL5 |
OC5C (Output Compare and PWM Output C for Timer/Counter5) |
|
|
PL4 |
OC5B (Output Compare and PWM Output B for Timer/Counter5) |
|
|
PL3 |
OC5A (Output Compare and PWM Output A for Timer/Counter5) |
|
|
PL2 |
T5 (Timer/Counter5 Clock Input) |
|
|
PL1 |
ICP5 (Timer/Counter5 Input Capture Trigger) |
|
|
PL0 |
ICP4 (Timer/Counter4 Input Capture Trigger) |
|
|
• OC5C – Port L, Bit 5
OC5C, Output Compare Match C output: The PL5 pin can serve as an external output for the Timer/Counter5 Output Compare C. The pin has to be configured as an output (DDL5 set) to serve this function. The OC5C pin is also the output pin for the PWM mode timer function.
• OC5B – Port L, Bit 4
OC5B, Output Compare Match B output: The PL4 pin can serve as an external output for the Timer/Counter 5 Output Compare B. The pin has to be configured as an output (DDL4 set) to serve this function. The OC5B pin is also the output pin for the PWM mode timer function.
• OC5A – Port L, Bit 3
OC5A, Output Compare Match A output: The PL3 pin can serve as an external output for the Timer/Counter 5 Output Compare A. The pin has to be configured as an output (DDL3 set) to serve this function. The OC5A pin is also the output pin for the PWM mode timer function.
• T5 – Port L, Bit 2
T5, Timer/Counter5 counter source.
• ICP5 – Port L, Bit 1
ICP5, Input Capture Pin 5: The PL1 pin can serve as an Input Capture pin for Timer/Counter5.
• ICP4 – Port L, Bit 0
ICP4, Input Capture Pin 4: The PL0 pin can serve as an Input Capture pin for Timer/Counter4.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] |
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Table 13-34 and Table 13-35 relates the alternate functions of Port L to the overriding signals shown in Figure 13- 5 on page 73.
Table 13-34. Overriding Signals for Alternate Functions in PL7:PL4
Signal Name |
PL7 |
PL6 |
PL5/OC5C |
PL4/OC5B |
|
|
|
|
|
PUOE |
0 |
0 |
0 |
0 |
|
|
|
|
|
PUOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DDOE |
– |
– |
0 |
0 |
|
|
|
|
|
DDOV |
– |
– |
0 |
0 |
|
|
|
|
|
PVOE |
– |
– |
OC5C ENABLE |
OC5B ENABLE |
|
|
|
|
|
PVOV |
– |
– |
OC5C |
OC5B |
|
|
|
|
|
PTOE |
– |
– |
– |
– |
|
|
|
|
|
DIEOE |
0 |
0 |
0 |
0 |
|
|
|
|
|
DIEOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DI |
0 |
0 |
0 |
0 |
|
|
|
|
|
AIO |
– |
– |
– |
– |
|
|
|
|
|
Table 13-35. Overriding Signals for Alternate Functions in PL3:PL0
Signal Name |
PL3/OC5A |
PL2/T5 |
PL1/ICP5 |
PL0/ICP4 |
|
|
|
|
|
PUOE |
0 |
0 |
0 |
0 |
|
|
|
|
|
PUOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DDOE |
0 |
0 |
0 |
0 |
|
|
|
|
|
DDOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
PVOE |
OC5A ENABLE |
0 |
0 |
0 |
|
|
|
|
|
PVOV |
OC5A |
0 |
0 |
0 |
|
|
|
|
|
PTOE |
– |
– |
– |
– |
|
|
|
|
|
DIEOE |
0 |
0 |
0 |
0 |
|
|
|
|
|
DIEOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DI |
0 |
T5 INPUT |
ICP5 INPUT |
ICP4 INPUT |
|
|
|
|
|
AIO |
– |
– |
– |
– |
|
|
|
|
|
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] |
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2549Q–AVR–02/2014
13.4Register Description for I/O-Ports
13.4.1MCUCR – MCU Control Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
0x35 (0x55) |
JTD |
– |
– |
PUD |
– |
– |
IVSEL |
IVCE |
MCUCR |
Read/Write |
R/W |
R |
R |
R/W |
R |
R |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the I/O ports pull-up resistors are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-up resistor ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 68 for more details about this feature.
13.4.2PORTA – Port A Data Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
0x02 (0x22) |
PORTA7 |
PORTA6 |
PORTA5 |
PORTA4 |
PORTA3 |
PORTA2 |
PORTA1 |
PORTA0 |
PORTA |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
13.4.3DDRA – Port A Data Direction Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
0x01 (0x21) |
DDA7 |
DDA6 |
DDA5 |
DDA4 |
DDA3 |
DDA2 |
DDA1 |
DDA0 |
DDRA |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
13.4.4PINA – Port A Input Pins Address
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
0x00 (0x20) |
PINA7 |
PINA6 |
PINA5 |
PINA4 |
PINA3 |
PINA2 |
PINA1 |
PINA0 |
PINA |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
|
13.4.5PORTB – Port B Data Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
0x05 (0x25) |
PORTB7 |
PORTB6 |
PORTB5 |
PORTB4 |
PORTB3 |
PORTB2 |
PORTB1 |
PORTB0 |
PORTB |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
13.4.6DDRB – Port B Data Direction Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
0x04 (0x24) |
DDB7 |
DDB6 |
DDB5 |
DDB4 |
DDB3 |
DDB2 |
DDB1 |
DDB0 |
DDRB |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
13.4.7PINB – Port B Input Pins Address
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
0x03 (0x23) |
PINB7 |
PINB6 |
PINB5 |
PINB4 |
PINB3 |
PINB2 |
PINB1 |
PINB0 |
PINB |
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
|
Initial Value |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
|
|
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] |
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2549Q–AVR–02/2014
13.4.8PORTC – Port C Data Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
0x08 (0x28) |
PORTC7 |
PORTC6 |
PORTC5 |
PORTC4 |
PORTC3 |
PORTC2 |
PORTC1 |
PORTC0 |
PORTC |
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
13.4.9DDRC – Port C Data Direction Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
0x07 (0x27) |
DDC7 |
DDC6 |
DDC5 |
DDC4 |
DDC3 |
DDC2 |
DDC1 |
DDC0 |
DDRC |
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
13.4.10PINC– Port C Input Pins Address
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
0x06 (0x26) |
PINC7 |
PINC6 |
PINC5 |
PINC4 |
PINC3 |
PINC2 |
PINC1 |
PINC0 |
PINC |
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
|
Initial Value |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
|
|
13.4.11PORTD – Port D Data Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
0x0B (0x2B) |
PORTD7 |
PORTD6 |
PORTD5 |
PORTD4 |
PORTD3 |
PORTD2 |
PORTD1 |
PORTD0 |
PORTD |
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
13.4.12DDRD – Port D Data Direction Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
0x0A (0x2A) |
DDD7 |
DDD6 |
DDD5 |
DDD4 |
DDD3 |
DDD2 |
DDD1 |
DDD0 |
DDRD |
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
13.4.13PIND – Port D Input Pins Address
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
0x09 (0x29) |
PIND7 |
PIND6 |
PIND5 |
PIND4 |
PIND3 |
PIND2 |
PIND1 |
PIND0 |
PIND |
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
|
Initial Value |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
|
|
13.4.14PORTE – Port E Data Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
0x0E (0x2E) |
PORTE7 |
PORTE6 |
PORTE5 |
PORTE4 |
PORTE3 |
PORTE2 |
PORTE1 |
PORTE0 |
PORTE |
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
13.4.15DDRE – Port E Data Direction Register
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
0x0D (0x2D) |
DDE7 |
DDE6 |
DDE5 |
DDE4 |
DDE3 |
DDE2 |
DDE1 |
DDE0 |
DDRE |
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] |
97 |
2549Q–AVR–02/2014