Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0
Signal |
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|
Name |
PC3/A11 |
PC2/A10 |
PC1/A9 |
PC0/A8 |
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|
PUOE |
SRE • (XMM<5) |
SRE • (XMM<6) |
SRE • (XMM<7) |
SRE • (XMM<7) |
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|
|
|
|
PUOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DDOE |
SRE • (XMM<5) |
SRE • (XMM<6) |
SRE • (XMM<7) |
SRE • (XMM<7) |
|
|
|
|
|
DDOV |
1 |
1 |
1 |
1 |
|
|
|
|
|
PVOE |
SRE • (XMM<5) |
SRE • (XMM<6) |
SRE • (XMM<7) |
SRE • (XMM<7) |
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|
|
|
|
PVOV |
A11 |
A10 |
A9 |
A8 |
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|
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|
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DIEOE |
0 |
0 |
0 |
0 |
|
|
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|
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DIEOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DI |
– |
– |
– |
– |
|
|
|
|
|
AIO |
– |
– |
– |
– |
|
|
|
|
|
13.3.4Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 13-12.
Table 13-12. Port D Pins Alternate Functions
Port Pin |
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Alternate Function |
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PD7 |
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T0 (Timer/Counter0 Clock Input) |
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PD6 |
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T1 (Timer/Counter1 Clock Input) |
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PD5 |
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XCK1 (USART1 External Clock Input/Output) |
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PD4 |
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ICP1 (Timer/Counter1 Input Capture Trigger) |
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PD3 |
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INT3/TXD1 (External Interrupt3 Input or USART1 Transmit Pin) |
||||||||
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PD2 |
|
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(External Interrupt2 Input or USART1 Receive Pin) |
INT2/RXD1 |
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PD1 |
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INT1/SDA (External Interrupt1 Input or TWI Serial DAta) |
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PD0 |
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INT0/SCL (External Interrupt0 Input or TWI Serial CLock) |
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The alternate pin configuration is as follows:
• T0 – Port D, Bit 7
T0, Timer/Counter0 counter source.
• T1 – Port D, Bit 6
T1, Timer/Counter1 counter source.
• XCK1 – Port D, Bit 5
XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1 operates in Synchronous mode.
• ICP1 – Port D, Bit 4
ICP1 – Input Capture Pin 1: The PD4 pin can act as an input capture pin for Timer/Counter1.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] |
80 |
2549Q–AVR–02/2014
• INT3/TXD1 – Port D, Bit 3
INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU.
TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3.
• INT2/RXD1 – Port D, Bit 2
INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU.
RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.
• INT1/SDA – Port D, Bit 1
INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the MCU.
SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.
• INT0/SCL – Port D, Bit 0
INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the MCU.
SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.
Table 13-13 on page 81 and Table 13-14 on page 82 relates the alternate functions of Port D to the overriding signals shown in Figure 13-5 on page 73.
Table 13-13. Overriding Signals for Alternate Functions PD7:PD4
Signal Name |
PD7/T0 |
PD6/T1 |
PD5/XCK1 |
PD4/ICP1 |
|
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PUOE |
0 |
0 |
0 |
0 |
|
|
|
|
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PUOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DDOE |
0 |
0 |
XCK1 OUTPUT ENABLE |
0 |
|
|
|
|
|
DDOV |
0 |
0 |
1 |
0 |
|
|
|
|
|
PVOE |
0 |
0 |
XCK1 OUTPUT ENABLE |
0 |
|
|
|
|
|
PVOV |
0 |
0 |
XCK1 OUTPUT |
0 |
|
|
|
|
|
DIEOE |
0 |
0 |
0 |
0 |
|
|
|
|
|
DIEOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DI |
T0 INPUT |
T1 INPUT |
XCK1 INPUT |
ICP1 INPUT |
|
|
|
|
|
AIO |
– |
– |
– |
– |
|
|
|
|
|
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] |
81 |
2549Q–AVR–02/2014
Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0(1)
Signal Name |
PD3/INT3/TXD1 |
PD2/INT2/RXD1 |
PD1/INT1/SDA |
PD0/INT0/SCL |
||||||
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|
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PUOE |
TXEN1 |
RXEN1 |
TWEN |
TWEN |
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PUOV |
0 |
PORTD2 • |
|
|
PORTD1 • |
|
|
PORTD0 • |
|
|
PUD |
PUD |
PUD |
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|
||||||
DDOE |
TXEN1 |
RXEN1 |
TWEN |
TWEN |
||||||
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|
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DDOV |
1 |
0 |
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SDA_OUT |
SCL_OUT |
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|
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PVOE |
TXEN1 |
0 |
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TWEN |
TWEN |
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PVOV |
TXD1 |
0 |
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|
0 |
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0 |
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|
||||||
DIEOE |
INT3 ENABLE |
INT2 ENABLE |
INT1 ENABLE |
INT0 ENABLE |
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DIEOV |
1 |
1 |
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|
1 |
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1 |
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||||||
DI |
INT3 INPUT |
INT2 INPUT/RXD1 |
INT1 INPUT |
INT0 INPUT |
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|
||||||
AIO |
– |
– |
SDA INPUT |
SCL INPUT |
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Note: 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module.
13.3.5Alternate Functions of Port E
The Port E pins with alternate functions are shown in Table 13-15.
Table 13-15. Port E Pins Alternate Functions
Port Pin |
Alternate Function |
|
|
|
|
PE7 |
INT7/ICP3/CLK0 |
|
(External Interrupt 7 Input, Timer/Counter3 Input Capture Trigger or Divided System Clock) |
||
|
||
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|
|
PE6 |
INT6/ T3 |
|
(External Interrupt 6 Input or Timer/Counter3 Clock Input) |
||
|
||
|
|
|
PE5 |
INT5/OC3C |
|
(External Interrupt 5 Input or Output Compare and PWM Output C for Timer/Counter3) |
||
|
||
|
|
|
PE4 |
INT4/OC3B |
|
(External Interrupt4 Input or Output Compare and PWM Output B for Timer/Counter3) |
||
|
||
|
|
|
PE3 |
AIN1/OC3A |
|
(Analog Comparator Negative Input or Output Compare and PWM Output A for Timer/Counter3) |
||
|
||
|
|
|
PE2 |
AIN0/XCK0 |
|
(Analog Comparator Positive Input or USART0 external clock input/output) |
||
|
||
|
|
|
PE1 |
PDO(1)/TXD0 |
|
(Programming Data Output or USART0 Transmit Pin) |
||
|
||
|
|
|
PE0 |
PDI(1)/RXD0/PCINT8 |
|
(Programming Data Input, USART0 Receive Pin or Pin Change Interrupt 8) |
||
|
||
|
|
Note: 1. Only for ATmega1281/2561. For ATmega640/1280/2560 these functions are placed on MISO/MOSI pins.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] |
82 |
2549Q–AVR–02/2014 |
|
• INT7/ICP3/CLKO – Port E, Bit 7
INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source.
ICP3, Input Capture Pin 3: The PE7 pin can act as an input capture pin for Timer/Counter3.
CLKO - Divided System Clock: The divided system clock can be output on the PE7 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTE7 and DDE7 settings. It will also be output during reset.
• INT6/T3 – Port E, Bit 6
INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source.
T3, Timer/Counter3 counter source.
• INT5/OC3C – Port E, Bit 5
INT5, External Interrupt source 5: The PE5 pin can serve as an External Interrupt source.
OC3C, Output Compare Match C output: The PE5 pin can serve as an External output for the Timer/Counter3 Output Compare C. The pin has to be configured as an output (DDE5 set “one”) to serve this function. The OC3C pin is also the output pin for the PWM mode timer function.
• INT4/OC3B – Port E, Bit 4
INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt source.
OC3B, Output Compare Match B output: The PE4 pin can serve as an External output for the Timer/Counter3 Output Compare B. The pin has to be configured as an output (DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function.
• AIN1/OC3A – Port E, Bit 3
AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator.
OC3A, Output Compare Match A output: The PE3 pin can serve as an External output for the Timer/Counter3 Output Compare A. The pin has to be configured as an output (DDE3 set “one”) to serve this function. The OC3A pin is also the output pin for the PWM mode timer function.
• AIN0/XCK0 – Port E, Bit 2
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator.
XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode.
• PDO/TXD0 – Port E, Bit 1
PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega1281/2561. For ATmega640/1280/2560 this function is placed on MISO.
TXD0, USART0 Transmit pin.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] |
83 |
2549Q–AVR–02/2014
• PDI/RXD0/PCINT8 – Port E, Bit 0
PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega1281/2561. For ATmega640/1280/2560 this function is placed on MOSI.
RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.
PCINT8, Pin Change Interrupt source 8: The PE0 pin can serve as an external interrupt source.
Table 13-16 on page 84 and Table 13-17 on page 84 relates the alternate functions of Port E to the overriding signals shown in Figure 13-5 on page 73.
Table 13-16. Overriding Signals for Alternate Functions PE7:PE4
Signal Name |
PE7/INT7/ICP3 |
PE6/INT6/T3 |
PE5/INT5/OC3C |
PE4/INT4/OC3B |
|
|
|
|
|
|
|
PUOE |
0 |
0 |
0 |
0 |
|
|
|
|
|
|
|
PUOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
|
|
DDOE |
0 |
0 |
0 |
0 |
|
|
|
|
|
|
|
DDOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
|
|
PVOE |
0 |
0 |
OC3C ENABLE |
OC3B ENABLE |
|
|
|
|
|
|
|
PVOV |
0 |
0 |
OC3C |
OC3B |
|
|
|
|
|
|
|
DIEOE |
INT7 ENABLE |
INT6 ENABLE |
INT5 ENABLE |
INT4 ENABLE |
|
|
|
|
|
|
|
DIEOV |
1 |
1 |
1 |
1 |
|
|
|
|
|
|
|
DI |
INT7 INPUT/ICP3 |
INT7 INPUT/T3 INPUT |
INT5 INPUT |
INT4 INPUT |
|
INPUT |
|||||
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||
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|
AIO |
– |
– |
– |
– |
|
|
|
|
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|
Table 13-17. Overriding Signals for Alternate Functions in PE3:PE0
Signal Name |
PE3/AIN1/OC3A |
PE2/AIN0/XCK0 |
PE1/PDO(1)/TXD0 |
PE0/PDI(1)/RXD0/PCINT8 |
|||
PUOE |
0 |
0 |
TXEN0 |
RXEN0 |
|||
|
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|
|
|
PUOV |
0 |
0 |
0 |
PORTE0 • |
|
|
|
PUD |
|||||||
|
|
|
|
|
|
|
|
DDOE |
0 |
XCK0 OUTPUT |
TXEN0 |
RXEN0 |
|||
ENABLE |
|||||||
|
|
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|
||
|
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|
|
|
DDOV |
0 |
1 |
1 |
0 |
|
|
|
|
|
|
|
|
|
|
|
PVOE |
OC3B ENABLE |
XCK0 OUTPUT |
TXEN0 |
0 |
|
|
|
ENABLE |
|
|
|||||
|
|
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||
|
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|
PVOV |
OC3B |
XCK0 OUTPUT |
TXD0 |
0 |
|
|
|
|
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|
|||
DIEOE |
0 |
0 |
0 |
PCINT8 • PCIE1 |
|||
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DIEOV |
0 |
0 |
0 |
1 |
|
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|
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|
|||
DI |
0 |
XCK0 INPUT |
– |
RXD0 |
|||
|
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|
|||
PE0 |
0 |
0 |
0 |
PCINT8 INPUT |
|||
|
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|
|||
AIO |
AIN1 INPUT |
AIN0 INPUT |
– |
– |
|||
|
|
|
|
|
|
|
|
Note: 1. PDO/PDI only available at PE1/PE0 for ATmega1281/2561.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] |
84 |
2549Q–AVR–02/2014