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Table 13-5.

Overriding Signals for Alternate Functions in PA3:PA0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal Name

 

 

 

 

PA3/AD3

 

 

 

PA2/AD2

 

 

 

PA1/AD1

 

 

 

PA0/AD0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PUOE

 

 

 

 

SRE

 

 

 

SRE

 

 

 

SRE

 

 

 

SRE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

~(

 

| ADA) • PORTA3

~(

 

| ADA) • PORTA2

~(

 

| ADA) • PORTA1

~(

 

| ADA) • PORTA0

 

 

PUOV

WR

WR

WR

WR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• PUD

 

 

 

• PUD

 

 

 

• PUD

 

 

 

• PUD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDOE

 

 

 

 

SRE

 

 

 

SRE

 

 

 

SRE

 

 

 

SRE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDOV

 

 

 

 

 

| ADA

 

 

 

 

| ADA

 

 

 

 

| ADA

 

 

 

 

| ADA

 

 

 

 

 

WR

 

 

WR

 

 

WR

 

 

WR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PVOE

 

 

 

 

SRE

 

 

 

SRE

 

 

 

SRE

 

 

 

SRE

 

 

 

 

 

 

 

 

 

 

PVOV

 

A3 • ADA | D3 OUTPUT

A2• ADA | D2 OUTPUT

A1 • ADA | D1 OUTPUT

A0 • ADA | D0 OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• WR

 

 

 

• WR

 

 

 

• WR

 

 

 

• WR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIEOE

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIEOV

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DI

 

 

 

D3 INPUT

 

 

D2 INPUT

 

 

D1 INPUT

 

 

D0 INPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13.3.2Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 13-6.

Table 13-6.

Port B Pins Alternate Functions

Port Pin

 

 

 

Alternate Functions

 

 

 

PB7

 

OC0A/OC1C/PCINT7 (Output Compare and PWM Output A for Timer/Counter0, Output Compare and

 

 

PWM Output C for Timer/Counter1 or Pin Change Interrupt 7)

 

 

 

 

 

 

PB6

 

OC1B/PCINT6 (Output Compare and PWM Output B for Timer/Counter1 or Pin Change Interrupt 6)

 

 

 

PB5

 

OC1A/PCINT5 (Output Compare and PWM Output A for Timer/Counter1 or Pin Change Interrupt 5)

 

 

 

PB4

 

OC2A/PCINT4 (Output Compare and PWM Output A for Timer/Counter2 or Pin Change Interrupt 4)

 

 

 

PB3

 

MISO/PCINT3 (SPI Bus Master Input/Slave Output or Pin Change Interrupt 3)

 

 

 

PB2

 

MOSI/PCINT2 (SPI Bus Master Output/Slave Input or Pin Change Interrupt 2)

 

 

 

PB1

 

SCK/PCINT1 (SPI Bus Serial Clock or Pin Change Interrupt 1)

 

 

 

 

PB0

 

 

 

 

 

 

SS/PCINT0 (SPI Slave Select input or Pin Change Interrupt 0)

 

 

 

 

 

The alternate pin configuration is as follows:

• OC0A/OC1C/PCINT7, Bit 7

OC0A, Output Compare Match A output: The PB7 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB7 set “one”) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC1C pin is also the output pin for the PWM mode timer function.

PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source.

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

76

2549Q–AVR–02/2014

• OC1B/PCINT6, Bit 6

OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

PCINT6, Pin Change Interrupt source 6: The PB6 pin can serve as an external interrupt source.

• OC1A/PCINT5, Bit 5

OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

PCINT5, Pin Change Interrupt source 5: The PB5 pin can serve as an external interrupt source.

• OC2A/PCINT4, Bit 4

OC2A, Output Compare Match output: The PB4 pin can serve as an external output for the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function.

PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt source.

• MISO/PCINT3 – Port B, Bit 3

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.

PCINT3, Pin Change Interrupt source 3: The PB3 pin can serve as an external interrupt source.

• MOSI/PCINT2 – Port B, Bit 2

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.

PCINT2, Pin Change Interrupt source 2: The PB2 pin can serve as an external interrupt source.

• SCK/PCINT1 – Port B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.

PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt source.

• SS/PCINT0 – Port B, Bit 0

SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

77

2549Q–AVR–02/2014

Table 13-7 and Table 13-8 relate the alternate functions of Port B to the overriding signals shown in Figure 13-5 on page 73. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source.

Table 13-7.

Overriding Signals for Alternate Functions in PB7:PB4

 

 

Signal Name

 

PB7/OC0A/OC1C

PB6/OC1B

 

PB5/OC1A

PB4/OC2A

 

 

 

 

 

 

 

PUOE

 

0

0

 

0

0

 

 

 

 

 

 

 

PUOV

 

0

0

 

0

0

 

 

 

 

 

 

 

DDOE

 

0

0

 

0

0

 

 

 

 

 

 

 

DDOV

 

0

0

 

0

0

 

 

 

 

 

 

 

PVOE

 

OC0/OC1C ENABLE

OC1B ENABLE

 

OC1A ENABLE

OC2A ENABLE

 

 

 

 

 

 

 

PVOV

 

OC0/OC1C

OC1B

 

OC1A

OC2A

 

 

 

 

 

 

 

DIEOE

 

PCINT7 • PCIE0

PCINT6 • PCIE0

 

PCINT5 • PCIE0

PCINT4 • PCIE0

 

 

 

 

 

 

 

DIEOV

 

1

1

 

1

1

 

 

 

 

 

 

 

DI

 

PCINT7 INPUT

PCINT6 INPUT

 

PCINT5 INPUT

PCINT4 INPUT

 

 

 

 

 

 

 

AIO

 

 

 

 

 

 

 

 

 

Table 13-8.

Overriding Signals for Alternate Functions in PB3:PB0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal Name

 

PB3/MISO

PB2/MOSI

 

PB1/SCK

 

 

 

 

 

 

 

 

 

PB0/SS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PUOE

 

SPE • MSTR

SPE •

 

 

 

 

 

 

SPE •

 

 

 

 

SPE •

 

 

 

 

 

 

 

 

MSTR

MSTR

MSTR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PUOV

 

PORTB3 •

 

 

 

PORTB2 •

 

 

 

 

 

PORTB1 •

 

 

 

PORTB0 •

 

 

 

 

 

PUD

PUD

PUD

PUD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDOE

 

SPE • MSTR

SPE •

 

 

 

 

 

SPE •

 

 

 

SPE •

 

 

 

 

 

 

 

MSTR

MSTR

MSTR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDOV

 

0

 

 

 

0

 

 

 

 

 

0

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PVOE

 

SPE •

 

 

 

SPE • MSTR

 

SPE • MSTR

0

 

 

 

 

 

 

MSTR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PVOV

 

SPI SLAVE OUTPUT

SPI MSTR OUTPUT

 

SCK OUTPUT

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIEOE

 

PCINT3 • PCIE0

PCINT2 • PCIE0

 

PCINT1 • PCIE0

PCINT0 • PCIE0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIEOV

 

1

 

 

 

1

 

 

 

 

 

1

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPI MSTR INPUT

SPI SLAVE INPUT

 

SCK INPUT

SPI

 

 

 

 

DI

SS

 

PCINT3 INPUT

PCINT2 INPUT

 

PCINT1 INPUT

PCINT0 INPUT

 

 

 

 

 

 

 

 

 

 

AIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

78

2549Q–AVR–02/2014

13.3.3Alternate Functions of Port C

The Port C alternate function is as follows:

Table 13-9.

Port C Pins Alternate Functions

 

Port Pin

 

 

Alternate Function

 

 

 

 

PC7

 

A15

(External Memory interface address bit 15)

 

 

 

 

PC6

 

A14

(External Memory interface address bit 14)

 

 

 

 

PC5

 

A13

(External Memory interface address bit 13)

 

 

 

 

PC4

 

A12

(External Memory interface address bit 12)

 

 

 

 

PC3

 

A11

(External Memory interface address bit 11)

 

 

 

 

PC2

 

A10

(External Memory interface address bit 10)

 

 

 

 

PC1

 

A9

(External Memory interface address bit 9)

 

 

 

 

PC0

 

A8

(External Memory interface address bit 8)

 

 

 

 

Table 13-10 and Table 13-11 on page 80 relate the alternate functions of Port C to the overriding signals shown in Figure 13-5 on page 73.

Table 13-10. Overriding Signals for Alternate Functions in PC7:PC4

Signal Name

PC7/A15

PC6/A14

PC5/A13

PC4/A12

 

 

 

 

 

PUOE

SRE • (XMM<1)

SRE • (XMM<2)

SRE • (XMM<3)

SRE • (XMM<4)

 

 

 

 

 

PUOV

0

0

0

0

 

 

 

 

 

DDOE

SRE • (XMM<1)

SRE • (XMM<2)

SRE • (XMM<3)

SRE • (XMM<4)

 

 

 

 

 

DDOV

1

1

1

1

 

 

 

 

 

PVOE

SRE • (XMM<1)

SRE • (XMM<2)

SRE • (XMM<3)

SRE • (XMM<4)

 

 

 

 

 

PVOV

A15

A14

A13

A12

 

 

 

 

 

DIEOE

0

0

0

0

 

 

 

 

 

DIEOV

0

0

0

0

 

 

 

 

 

DI

 

 

 

 

 

AIO

 

 

 

 

 

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

79

2549Q–AVR–02/2014