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31.5System and Reset Characteristics

Table 31-3. Reset, Brown-out and Internal voltage CharacteristicsCharacteristics

Symbol

 

Parameter

Condition

Min

Typ

Max

Units

 

 

 

 

 

 

 

 

 

VRST

 

 

Pin Threshold Voltage

 

0.2VCC

 

0.9VCC

V

 

RESET

 

 

tRST

 

Minimum pulse width on

 

Pin

 

 

 

2.5

µs

 

RESET

 

 

 

VHYST

 

Brown-out Detector Hysteresis

 

 

50

 

mV

tBOD

 

Min Pulse Width on Brown-out Reset

 

 

2

 

µs

VBG

 

Bandgap reference voltage

VCC=2.7V, TA= 25 C

1.0

1.1

1.2

V

tBG

 

Bandgap reference start-up time

VCC=2.7V, TA= 25 C

 

40

70

µs

IBG

 

Bandgap reference current consumption

VCC=2.7V, TA= 25 C

 

10

 

µA

Note: 1.

The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).

 

 

31.5.1Standard Power-On Reset

This implementation of power-on reset existed in early versions of ATmega640/1280/1281/2560/2561. The table below describes the characteristics of this power-on reset and it is valid for the following devices only:

ATmega640: revision A

ATmega1280: revision A

ATmega1281: revision A

ATmega2560: revision A to E

ATmega2561: revision A to E

Table 31-4. Characteristics of Standard Power-On Reset. TA= -40 to +85°C.

Symbol

Parameter

Min.(1)

Typ.(1)

Max.(1)

Units

VPOT

Power-on Reset Threshold Voltage (rising)(2)

0.7

1.0

1.4

V

Power-on Reset Threshold Voltage (falling)(3)

0.05

0.9

1.3

V

 

VPSR

Power-on slope rate

0.01

 

4.5

V/ms

Notes: 1. Values are guidelines only.

2.Threshold where device is released from reset when voltage is rising.

3.The power-on reset threshold voltage (falling) will not work unless the supply voltage has been below VPOT.

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

360

2549Q–AVR–02/2014

31.5.2Enhanced Power-On Reset

This implementation of power-on reset exists in newer versions of ATmega640/1280/1281/2560/2561. The table below describes the characteristics of this power-on reset and it is valid for the following devices only:

ATmega640: revision B and newer

ATmega1280: revision B and newer

ATmega1281: revision B and newer

ATmega2560: revision F and newer

ATmega2561: revision F and newer

Table 31-5. Characteristics of Enhanced Power-On Reset. TA= -40 to +85°C.

Symbol

Parameter

Min.(1)

Typ.(1)

Max.(1)

Units

VPOT

Power-on Reset Threshold Voltage (rising)(2)

1.1

1.4

1.6

V

Power-on Reset Threshold Voltage (falling)(3)

0.6

1.3

1.6

V

 

VPSR

Power-On Slope Rate

0.01

 

 

V/ms

Notes: 1. Values are guidelines only.

2.Threshold where device is released from reset when voltage is rising.

3.The power-on reset threshold voltage (falling) will not work unless the supply voltage has been below VPOT.

Table 31-6. BODLEVEL Fuse Coding(1)

BODLEVEL 2:0 Fuses

Min. VBOT

Typ. VBOT

 

Max. VBOT

Units

111

 

BOD Disabled

 

 

 

 

 

 

 

110

1.7

1.8

 

2.0

 

 

 

 

 

 

 

101

2.5

2.7

 

2.9

V

 

 

 

 

 

 

100

4.1

4.3

 

4.5

 

 

 

 

 

 

 

011

 

 

 

 

 

 

 

 

 

 

 

010

 

Reserved

 

 

 

 

 

 

001

 

 

 

 

 

 

 

 

 

 

 

 

 

 

000

 

 

 

 

 

 

 

 

 

 

 

Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 for 4MHz operation of ATmega640V/1280V/1281V/2560V/2561V, BODLEVEL = 101 for 8MHz operation of ATmega640V/1280V/1281V/2560V/2561V and ATmega640/1280/1281, and BODLEVEL = 100 for 16MHz operation of ATmega640/1280/1281/2560/2561.

31.62-wire Serial Interface Characteristics

Table 31-7 on page 362 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega640/1280/1281/2560/2561 2-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 31-6 on page 363.

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

361

2549Q–AVR–02/2014

Table 31-7. 2-wire Serial Bus Requirements

Symbol

Parameter

 

Condition

 

 

Min.

 

Max.

Units

 

 

 

 

 

 

 

 

 

 

 

VIL

Input Low-voltage

 

 

 

 

 

-0.5

 

0.3 VCC

 

VIH

Input High-voltage

 

 

 

 

 

0.7 VCC

 

VCC + 0.5

V

 

 

 

 

 

 

 

 

 

 

Vhys(1)

Hysteresis of Schmitt Trigger Inputs

 

 

 

 

 

0.05 VCC(2)

 

 

 

 

 

 

 

 

(1)

Output Low-voltage

3mA sink current

 

0

 

0.4

 

VOL

 

 

 

(1)

Rise Time for both SDA and SCL

 

 

 

 

 

20 +

 

300

 

tr

 

 

 

 

 

0.1C (3)(2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b

 

 

 

(1)

Output Fall Time from VIHmin to VILmax

 

 

 

(3)

20 +

 

250

ns

tof

10pF < Cb < 400pF

 

0.1C (3)(2)

 

 

 

 

 

 

 

 

 

b

 

 

 

tSP(1)

Spikes Suppressed by Input Filter

 

 

 

 

 

0

 

50(2)

 

Ii

Input Current each I/O Pin

0.1VCC < Vi < 0.9VCC

-10

 

10

µA

C (1)

Capacitance for each I/O Pin

 

 

 

 

 

 

10

pF

i

 

 

 

 

 

 

 

 

 

 

 

 

f

(4) > max(16f

SCL

,

 

 

 

 

fSCL

SCL Clock Frequency

CK

250kHz)(5)

 

0

 

400

kHz

 

 

 

 

 

 

fSCL 100kHz

 

VCC 0.4V

 

1000ns

 

 

 

 

 

 

 

 

----------------------------

 

-------------------

 

Rp

Value of Pull-up resistor

 

 

 

 

 

3mA

 

Cb

 

fSCL > 100kHz

 

VCC 0.4V

 

300 ns

 

 

 

 

 

 

 

 

 

 

 

 

----------------------------

 

-----------------

 

 

 

 

 

 

 

 

3mA

 

Cb

 

tHD;STA

Hold Time (repeated) START Condition

fSCL 100kHz

 

4.0

 

 

 

 

 

 

 

 

 

 

 

fSCL > 100kHz

 

0.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

f

 

100kHz(6)

 

4.7

 

 

tLOW

Low Period of the SCL Clock

SCL

 

 

 

 

 

 

 

fSCL > 100kHz(7)

 

1.3

 

 

 

 

 

 

 

tHIGH

High period of the SCL clock

fSCL 100kHz

 

4.0

 

 

 

 

 

 

 

 

 

 

 

fSCL > 100kHz

 

0.6

 

 

 

 

 

 

 

tSU;STA

Set-up time for a repeated START condition

fSCL 100kHz

 

4.7

 

 

 

 

 

 

 

 

 

 

 

fSCL > 100kHz

 

0.6

 

µs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHD;DAT

Data hold time

fSCL 100kHz

 

0

 

3.45

 

 

 

fSCL > 100kHz

 

0

 

0.9

 

 

 

 

 

 

 

 

 

tSU;DAT

Data setup time

fSCL 100kHz

 

250

 

 

 

 

 

 

 

 

 

 

 

fSCL > 100kHz

 

100

 

 

 

 

 

 

 

tSU;STO

Setup time for STOP condition

fSCL 100kHz

 

4.0

 

 

 

 

 

 

 

 

 

 

 

fSCL > 100kHz

 

0.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tBUF

Bus free time between a STOP and START

fSCL 100kHz

 

4.7

 

 

condition

fSCL > 100kHz

 

1.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: 1.

In ATmega640/1280/1281/2560/2561, this parameter is characterized and not 100% tested.

 

 

2.Required only for fSCL > 100kHz.

3.Cb = capacitance of one bus line in pF.

4.fCK = CPU clock frequency.

5.This requirement applies to all ATmega640/1280/1281/2560/2561 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement.

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

362

2549Q–AVR–02/2014

6.The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz.

7.The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still, ATmega640/1280/1281/2560/2561 devices connected to the bus may communicate at full speed (400kHz) with

other ATmega640/1280/1281/2560/2561 devices, as well as any other device with a proper tLOW acceptance margin.

Figure 31-6. 2-wire Serial Bus Timing

 

 

 

 

 

 

 

 

 

 

 

 

 

tof

 

 

tHIGH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCL

 

 

 

 

 

 

 

 

 

 

 

 

tLOW

 

 

 

 

tLOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSU;STA

 

 

 

 

 

 

 

 

 

 

tHD;STA

 

tHD;DAT

 

 

 

 

 

 

t

 

 

 

 

 

 

 

SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SU;DAT

 

 

 

 

tSU;STO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tBUF

31.7SPI Timing Characteristics

See Figure 31-7 and Figure 31-8 on page 364 for details.

Table 31-8. SPI Timing Parameters

 

 

 

 

 

Description

Mode

Min.

Typ.

Max.

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

SCK period

Master

 

See Table 21-5 on page 198

 

 

 

 

 

 

 

 

 

 

 

2

 

 

SCK high/low

Master

 

50% duty cycle

 

 

 

 

 

 

 

 

 

 

 

3

 

 

Rise/Fall time

Master

 

3.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

Setup

Master

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

Hold

Master

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

Out to SCK

Master

 

0.5 • tsck

 

 

7

 

 

 

 

SCK to out

Master

 

10

 

 

 

 

 

 

 

 

 

 

8

 

SCK to out high

Master

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

low to out

Slave

 

15

 

 

 

 

 

SS

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

SCK period

Slave

4 • tck

 

 

 

 

 

 

 

 

 

11

 

SCK high/low(1)

Slave

2 • tck

 

 

 

12

 

 

Rise/Fall time

Slave

 

 

1600

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

Setup

Slave

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

Hold

Slave

tck

 

 

 

15

 

 

 

 

SCK to out

Slave

 

15

 

 

 

 

 

 

 

 

 

 

 

 

16

 

SCK to

 

high

Slave

20

 

 

 

SS

 

 

 

17

 

 

 

 

high to tri-state

Slave

 

10

 

 

 

SS

 

 

 

 

 

 

 

 

 

 

 

 

 

18

 

 

 

 

 

low to SCK

Slave

20

 

 

 

 

 

SS

 

 

 

Note:

1. In SPI Programming mode the minimum SCK high/low period is:

 

 

-2 tCLCL for fCK < 12MHz

-3 tCLCL for fCK > 12MHz

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

363

2549Q–AVR–02/2014

Figure 31-7. SPI Interface Timing Requirements (Master Mode)

SS

SCK (CPOL = 0)

SCK (CPOL = 1)

MISO

(Data Input)

MOSI

(Data Output)

6

 

 

1

 

 

2

2

4

5

 

3

 

MSB

...

LSB

 

 

7

8

 

MSB

...

LSB

Figure 31-8. SPI Interface Timing Requirements (Slave Mode)

SS

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

(Data Input)

MISO

(Data Output)

9

 

 

10

16

 

 

 

 

 

 

11

11

 

13

14

 

 

12

 

MSB

...

LSB

 

 

 

15

 

17

 

MSB

...

LSB

X

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

364

2549Q–AVR–02/2014