
- •Ethernet Controller Features
- •Buffer
- •Physical Layer (PHY) Features
- •Operational
- •Package Types
- •Table of Contents
- •Most Current Data Sheet
- •Errata
- •Customer Notification System
- •1.0 Overview
- •FIGURE 1-1: ENC28J60 Block Diagram
- •FIGURE 1-2: Typical ENC28J60 Based Interface
- •2.0 External Connections
- •2.1 Oscillator
- •FIGURE 2-1: Crystal Oscillator Operation
- •2.3 CLKOUT Pin
- •FIGURE 2-3: CLKOUT Transition
- •2.4 Magnetics, Termination and Other External Components
- •FIGURE 2-4: ENC28J60 Ethernet Termination and External Connections
- •2.5 I/O Levels
- •2.6 LED Configuration
- •3.0 Memory Organization
- •3.1 Control Registers
- •3.1.1 ECON1 Register
- •3.1.2 ECON2 Register
- •Register 3-2: ECON2: Ethernet Control Register 2
- •3.2 Ethernet Buffer
- •3.2.1 Receive Buffer
- •3.2.2 Transmit Buffer
- •3.2.3 Reading and Writing to the Buffer
- •3.2.4 DMA Access to the Buffer
- •FIGURE 3-2: Ethernet Buffer Organization
- •3.3 PHY Registers
- •3.3.1 Reading PHY Registers
- •3.3.2 Writing PHY Registers
- •3.3.3 Scanning a PHY Register
- •Register 3-3: MICMD: MII Command Register
- •3.3.4 PHSTAT Registers
- •3.3.5 PHID1 and PHID2 Registers
- •4.0 Serial Peripheral Interface (SPI)
- •4.1 Overview
- •FIGURE 4-2: SPI Output Timing
- •4.2 SPI Instruction Set
- •4.2.1 Read Control Register Command
- •FIGURE 4-3: Read Control Register Command Sequence (ETH Registers)
- •FIGURE 4-4: Read Control Register Command Sequence (MAC and MII Registers)
- •4.2.2 Read Buffer Memory Command
- •4.2.3 Write Control Register Command
- •FIGURE 4-5: Write Control Register Command Sequence
- •4.2.4 Write Buffer Memory Command
- •4.2.5 Bit Field Set Command
- •4.2.6 Bit Field Clear Command
- •FIGURE 4-6: Write Buffer Memory Command Sequence
- •4.2.7 System Reset Command
- •FIGURE 4-7: System Reset Command Sequence
- •5.0 Ethernet Overview
- •5.1 Packet Format
- •5.1.2 Destination Address
- •5.1.3 Source Address
- •5.1.4 Type/Length
- •5.1.5 Data
- •5.1.6 Padding
- •6.0 Initialization
- •6.1 Receive Buffer
- •6.2 Transmit Buffer
- •6.3 Receive Filters
- •6.4 Waiting for OST
- •6.5 MAC Initialization Settings
- •Register 6-3: MACON4: MAC Control Register 4
- •Register 6-4: MABBIPG: MAC Back-to-back Inter-packet GAP Register
- •6.6 PHY Initialization Settings
- •7.0 Transmitting and Receiving Packets
- •7.1 Transmitting Packets
- •7.2 Receiving Packets
- •7.2.1 Enabling Reception
- •7.2.2 Receive Packet Layout
- •FIGURE 7-3: Sample Receive Packet Layout
- •7.2.3 Reading Received Packets
- •EXAMPLE 7-1: Random Access Address Calculation
- •7.2.4 Freeing Receive Buffer Space
- •7.2.5 Receive Buffer Free Space
- •EXAMPLE 7-2: Receive Buffer Free Space Calculation
- •8.0 Receive Filters
- •Register 8-1: ERXFCON: Ethernet RECEIVE FILTER CONTROL REGISTER
- •FIGURE 8-1: Receive Filtering Using OR Logic
- •FIGURE 8-2: Receive Filtering Using AND Logic
- •8.1 Unicast Filter
- •8.2 Pattern Match Filter
- •FIGURE 8-3: Sample Pattern Match Format
- •8.3 Magic Packet™ Filter
- •FIGURE 8-4: SAMPLE MAGIC PACKET™ Format
- •8.4 Hash Table Filter
- •8.5 Multicast Filter
- •8.6 Broadcast Filter
- •9.0 Duplex Mode Configuration and Negotiation
- •10.0 Flow Control
- •FIGURE 10-1: Sample Full-Duplex Network
- •Register 10-1: EFLOCON: Ethernet Flow Control Register
- •TABLE 10-1: Summary of Registers Used with Flow Control
- •11.0 Reset
- •FIGURE 11-1: On-Chip Reset Circuit
- •11.2 System Reset
- •11.3 Transmit Only Reset
- •11.4 Receive Only Reset
- •11.5 PHY Subsystem Reset
- •Register 11-1: PHCON1: PHY Control Register 1
- •12.0 Interrupts
- •FIGURE 12-1: ENC28J60 Interrupt Logic
- •12.1 INT Interrupt Enable (INTIE)
- •12.1.1 INT Interrupt Registers
- •Register 12-1: ESTAT: Ethernet Status Register
- •Register 12-2: EIE: Ethernet Interrupt Enable Register
- •Register 12-3: EIR: Ethernet Interrupt Request (Flag) Register
- •Register 12-4: PHIE: PHY Interrupt Enable Register
- •Register 12-5: PHIR: PHY Interrupt Request (Flag) Register
- •12.1.2 Receive Error Interrupt Flag (RXERIF)
- •12.1.3 Transmit Error Interrupt Flag (TXERIF)
- •12.1.4 Transmit Interrupt Flag (TXIF)
- •12.1.5 Link Change Interrupt Flag (LINKIF)
- •12.1.6 DMA Interrupt Flag (DMAIF)
- •12.1.7 Receive Packet Pending Interrupt Flag (PKTIF)
- •12.2.1 Setup Steps for Waking Up on a Magic Packet
- •13.0 Direct Memory Access Controller
- •13.1 Copying Memory
- •13.2 Checksum Calculations
- •TABLE 13-1: Summary of Registers Associated with the DMA Controller
- •14.0 Power-Down
- •TABLE 14-1: Summary of Registers Used with Power-Down
- •Register 15-1: EBSTCON: Ethernet SELF-TEST CONTROL REGISTER
- •15.1 Using the BIST
- •15.2 Random Data Fill Mode
- •15.3 Address Fill Mode
- •15.4 Pattern Shift Fill Mode
- •16.0 Electrical Characteristics
- •Absolute Maximum Ratings
- •16.1 DC Characteristics: ENC28J60 (Industrial and Commercial)
- •TABLE 16-1: AC Characteristics: ENC28J60 (Industrial and Commercial)
- •TABLE 16-2: Oscillator Timing Characteristics
- •TABLE 16-3: Reset AC Characteristics
- •TABLE 16-4: CLKOUT Pin AC Characteristics
- •TABLE 16-5: Requirements for External Magnetics
- •FIGURE 16-2: SPI Output Timing
- •TABLE 16-6: SPI Interface AC Characteristics
- •17.0 Packaging Information
- •17.1 Package Marking Information
- •17.2 Package Details
- •Appendix A: Revision History
- •Revision A (January 2006)
- •Revision B (July 2006)
- •Revision C (January 2008)
- •Revision D (July 2012)
- •Revision E (November 2012)
- •The Microchip Web Site
- •Customer Change Notification Service
- •Customer Support
- •Reader Response
- •INDEX
- •Product Identification System
- •Worldwide Sales and Service

ENC28J60
8.0RECEIVE FILTERS
To minimize the processing requirements of the host controller, the ENC28J60 incorporates several different receive filters which can automatically reject packets which are not needed. Six different types of packet filters are implemented:
•Unicast
•Pattern Match
•Magic Packet™
•Hash Table
•Multicast
•Broadcast
The individual filters are all configured by the ERXFCON register (Register 8-1). More than one filter can be active at any given time. Additionally, the filters can be configured by the ANDOR bit to either logically AND, or logically OR, the tests of several filters. In other words, the filters may be set so that only packets accepted by all active filters are accepted, or a packet accepted by any one filter is accepted. The flowcharts in Figure 8-1 and Figure 8-2 show the effect that each of the filters will have depending on the setting of ANDOR.
The device can enter Promiscuous mode and receive all packets by clearing the ERXFCON register. The proper setting of the register will depend on the application requirements.
2006-2012 Microchip Technology Inc. |
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DS39662E-page 47 |

ENC28J60
REGISTER 8-1: ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER
R/W-1 |
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R/W-0 |
R/W-1 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-1 |
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UCEN |
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ANDOR |
CRCEN |
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PMEN |
MPEN |
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HTEN |
MCEN |
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BCEN |
bit 7 |
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bit 0 |
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Legend: |
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R = Readable bit |
W = Writable bit |
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U = Unimplemented bit, read as ‘0’ |
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-n = Value at POR |
‘1’ = Bit is set |
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‘0’ = Bit is cleared |
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x = Bit is unknown |
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bit 7 |
UCEN: Unicast Filter Enable bit |
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When ANDOR = 1: |
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1 |
= Packets not having a destination address matching the local MAC address will be discarded |
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0 |
= Filter disabled |
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When ANDOR = 0: |
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1 |
= Packets with a destination address matching the local MAC address will be accepted |
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0 |
= Filter disabled |
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bit 6 |
ANDOR: AND/OR Filter Select bit |
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1 |
= AND: Packets will be rejected unless all enabled filters accept the packet |
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0 |
= OR: Packets will be accepted unless all enabled filters reject the packet |
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bit 5 |
CRCEN: Post-Filter CRC Check Enable bit |
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1 |
= All packets with an invalid CRC will be discarded |
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0 |
= The CRC validity will be ignored |
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bit 4 |
PMEN: Pattern Match Filter Enable bit |
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When ANDOR = 1: |
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1 |
= Packets must meet the Pattern Match criteria or they will be discarded |
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0 |
= Filter disabled |
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When ANDOR = 0: |
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1 |
= Packets which meet the Pattern Match criteria will be accepted |
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0 |
= Filter disabled |
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bit 3 |
MPEN: Magic Packet™ Filter Enable bit |
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When ANDOR = 1: |
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1 |
= Packets must be Magic Packets for the local MAC address or they will be discarded |
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0 |
= Filter disabled |
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When ANDOR = 0: |
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1 |
= Magic Packets for the local MAC address will be accepted |
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0 |
= Filter disabled |
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bit 2 |
HTEN: Hash Table Filter Enable bit |
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When ANDOR = 1: |
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1 |
= Packets must meet the Hash Table criteria or they will be discarded |
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0 |
= Filter disabled |
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When ANDOR = 0: |
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1 |
= Packets which meet the Hash Table criteria will be accepted |
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0 |
= Filter disabled |
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bit 1 |
MCEN: Multicast Filter Enable bit |
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When ANDOR = 1: |
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1 |
= Packets must have the Least Significant bit set in the destination address or they will be discarded |
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0 |
= Filter disabled |
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When ANDOR = 0: |
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1 |
= Packets which have the Least Significant bit set in the destination address will be accepted |
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0 |
= Filter disabled |
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bit 0 |
BCEN: Broadcast Filter Enable bit |
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When ANDOR = 1: |
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1 |
= Packets must have a destination address of FF-FF-FF-FF-FF-FF or they will be discarded |
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0 |
= Filter disabled |
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When ANDOR = 0: |
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1 |
= Packets which have a destination address of FF-FF-FF-FF-FF-FF will be accepted |
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0 |
= Filter disabled |
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DS39662E-page 48 |
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2006-2012 Microchip Technology Inc. |

ENC28J60
FIGURE 8-1: RECEIVE FILTERING USING OR LOGIC
Packet Detected on Wire, |
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ANDOR = 0 (OR) |
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UCEN, PMEN, |
Yes |
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MPEN, HTEN, |
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MCEN and BCEN |
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all clear? |
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No |
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UCEN set? |
Yes |
Unicast |
Yes |
CRCEN set? |
No |
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packet? |
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No |
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No |
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Yes |
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Yes |
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Yes |
CRCEN valid? |
Yes |
Accept Packet |
PMEN set? |
Pattern |
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matches? |
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No |
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No |
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No |
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Reject Packet |
MPEN set? |
Yes |
Magic Packet™ |
Yes |
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for us? |
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No |
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No |
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HTEN set? |
Yes |
Hash table |
Yes |
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bit set? |
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No |
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No |
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MCEN set? |
Yes |
Multicast |
Yes |
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destination? |
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No |
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No |
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BCEN set? |
Yes |
Broadcast |
Yes |
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destination? |
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No |
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No |
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2006-2012 Microchip Technology Inc. |
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. |
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DS39662E-page 49 |

ENC28J60
FIGURE 8-2: RECEIVE FILTERING USING AND LOGIC
Packet Detected on Wire |
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ANDOR = 1 (AND) |
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UCEN set? |
Yes |
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Unicast |
No |
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packet? |
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No |
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Yes |
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PMEN set? |
Yes |
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Pattern |
No |
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matches? |
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No |
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Yes |
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MPEN set? |
Yes |
Magic Packet™ |
No |
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for us? |
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No |
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Yes |
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HTEN set? |
Yes |
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Hash Table |
No |
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bit set? |
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No |
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Yes |
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MCEN set? |
Yes |
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Multicast |
No |
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destination? |
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No |
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Yes |
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BCEN set? |
Yes |
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Broadcast |
No |
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destination? |
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No |
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Yes |
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No |
CRCEN set? |
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Yes |
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CRC valid? |
No |
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Yes |
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Accept Packet |
Reject Packet |
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DS39662E-page 50 |
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2006-2012 Microchip Technology Inc. |