[AK4493]
■ Timing Diagram
MCLK |
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1/fCLK |
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VIH |
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VIL |
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tCLKH |
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tCLKL |
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dCLK=tCLKH x fCLK, tCLKL x fCLK |
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1/fs
VIH
VIL
LRCK
tLRH |
tLRL |
tBCK
VIH
BICK
VIL
tBCKH |
tBCKL |
tWCK
VIH
WCK
VIL
tWCKH |
tWCKL |
tB
VIH
BCK
VIL
tBH |
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tBL |
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Figure 13. Clock Timing
017012230-E-00 |
2017/12 |
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- 30 - |
[AK4493]
VIH
LRCK
VIL
tBLR tLRB
VIH
BICK
VIL
tSDS tSDH
VIH
SDATA
VIL
Figure 14. Audio Interface Timing (PCM Mode)
VIH
WCK
VIL
tBW |
tWB |
VIH
BCK
VIL
tDS |
tDH |
DINL |
VIH |
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DINR |
VIL |
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Figure 15. Audio Interface Timing (External Digital Filter I/F Mode)
017012230-E-00 |
2017/12 |
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- 31 - |
[AK4493]
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tDCK |
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tDCKL |
tDCKH |
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DCLK |
VIH |
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VIL |
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tDDD |
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DSDL |
VIH |
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DSDR |
VIL |
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tDDD |
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DSDL |
VIH |
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DSDR |
VIL |
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DSD Audio Interface Timing (DSD64, DSD128, DSD256 Mode) |
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tDCK |
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tDCKL |
tDCKH |
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DCLK |
VIH |
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VIL |
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tDDS |
tDDH |
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DSDL |
VIH |
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DSDR |
VIL |
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DSD Audio Interface Timing (DSD512 Mode)
Figure 16. Audio Interface Timing (DSD Normal Mode, DCKB bit = “0”)
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tDCK |
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tDCKL |
tDCKH |
DCLK |
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VIH |
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VIL |
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tDDD |
tDDD |
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DSDL |
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VIH |
DSDR |
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VIL |
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tDDD |
tDDD |
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DSDL |
VIH |
DSDR |
VIL |
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Figure 17. Audio Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
017012230-E-00 |
2017/12 |
- 32 -
[AK4493]
VIH
CSN
VIL
tCSS |
tCCKL tCCKH |
tCCK |
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VIH
CCLK
VIL
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tCDS |
tCDH |
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VIH |
CDTI |
C1 |
C0 |
R/W |
A4 |
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VIL |
Figure 18. WRITE Command Input Timing
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tCSW |
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VIH |
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CSN |
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VIL |
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tCSH |
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VIH
CCLK
VIL
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VIH |
CDTI |
D3 |
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D2 |
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D1 |
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D0 |
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VIL |
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Figure 19. WRITE Data Input Timing
017012230-E-00 |
2017/12 |
|
- 33 - |
[AK4493]
SDA |
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tBUF |
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tLOW |
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tR |
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tHIGH |
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tF |
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SCL |
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tHD:STA |
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tHD:DAT |
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tSU:DAT tSU:STA |
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Stop Start |
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Start |
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VIH |
VIL |
tSP |
VIH |
VIL |
tSU:STO |
Stop |
Figure 20. I2C Bus Mode Timing
tAPD tRPD
PDN
VIL
Figure 21. Power Down & Reset Timing
017012230-E-00 |
2017/12 |
|
- 34 - |