[AK4493]
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5. Pull-up, Pull-down Pin List |
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Classification |
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Pin Name |
Internal connection |
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pull-up pin (typ = 100kΩ) |
PSN |
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TVSS |
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pull-down pin(typ = 100kΩ) |
DZFL, DZFR, TESTE |
DVSS |
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6. Absolute Maximum Ratings |
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(AVSS = DVSS = VSSL = VSSR = VREFLL = VREFLR = 0V; Note 4) |
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Parameter |
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Symbol |
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Min. |
Max. |
Unit |
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Digital I/O |
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TVDD |
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4.0 |
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V |
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0.3 |
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Digital Core |
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DVDD |
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0.3 |
2.5 |
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V |
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Clock Interface |
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AVDD |
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0.3 |
4.0 |
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V |
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Analog |
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VDDL/R |
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6.0 |
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V |
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GND |
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0.3 |
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Power |
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|AVSS |
DVSS| |
(Note 5) |
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0.3 |
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V |
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GND |
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Supplies: |
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|AVSS VSSL| |
(Note 5) |
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0.3 |
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V |
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|AVSS VSSR| |
(Note 5) |
GND |
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- |
0.3 |
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V |
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|DVSS VSSL| |
(Note 5) |
GND |
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- |
0.3 |
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V |
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|DVSS VSSR| |
(Note 5) |
GND |
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- |
0.3 |
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V |
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|VSSL VSSR| |
(Note 5) |
GND |
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- |
0.3 |
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V |
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Voltage |
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“H” voltage reference |
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VREFHL/R |
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-0.3 |
VDDL/R+0.3 |
V |
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(Note 6) |
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Or 6.0 |
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Reference |
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“L” voltage reference |
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VREFLL/R |
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-0.3 |
+0.3 |
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V |
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Input Current, Any Pin Except Supplies |
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IIN |
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- |
10 |
mA |
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Digital Input Voltage |
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VIND |
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0.3 |
TVDD+0.3 |
V |
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(Note 7) |
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or 4.0 |
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Ambient Temperature (Power supplied) |
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Ta |
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40 |
85 |
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C |
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Storage Temperature |
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Tstg |
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65 |
150 |
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C |
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Note 4. All voltages with respect to ground.
Note 5. AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. Note 6. Regarding VREFHL/R pins, maximum value which is lower value (VDDL/R+0.3) or 6.0V. Note 7. Regarding Digital input pins, maximum value which is lower value (VDDL/R+0.3) or 4.0V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
017012230-E-00 |
2017/12 |
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- 10 - |
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[AK4493] |
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7. Recommended Operating Conditions |
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(AVSS = DVSS = VSSL = VSSR = VREFLL = VREFLR = 0V; Note 4) |
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Parameter |
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Symbol |
Min. |
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Typ. |
Max. |
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Unit |
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■ LDOE pin = “L” |
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Digital I/O |
TVDD |
DVDD |
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1.8 |
3.6 |
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V |
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Clock Interface |
AVDD |
DVDD |
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1.8 |
3.6 |
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V |
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Power Supplies |
Digital Core |
DVDD |
1.7 |
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1.8 |
1.98 |
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V |
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Analog |
VDDL/R |
4.75 |
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5.0 |
5.25 |
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V |
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(Note 8) |
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■ LDOE pin = “H” |
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Digital I/O |
TVDD |
3.0 |
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3.3 |
3.6 |
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V |
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Clock Interface |
AVDD |
3.0 |
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3.3 |
3.6 |
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V |
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Analog |
VDDL/R |
4.75 |
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5.0 |
5.25 |
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V |
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Voltage Reference |
“H” voltage reference |
VREFHL/R |
VDDL/R-0.5 |
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- |
VDDL/R |
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V |
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(Note 8) |
“L” voltage reference |
VREFLL/R |
- |
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VSSL/R |
- |
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V |
Note 4. All voltages with respect to ground.
Note 8. The analog output voltage scales with the voltage of (VREFHL/R VREFLL/R).
Note 9. TVDD must be powered up before AVDD or at the same time. When not using the internal LDO (LDOE pin = “L”), TVDD must be powered up before DVDD or at the same time.
Note 10. The internal LDO outputs DVDD (1.8V) when the LDOE pin = “H”.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
017012230-E-00 |
2017/12 |
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- 11 - |