[AK4493]

■ Power-OFF/Reset Function

Power-off and Reset function of the AK4493 are controlled by PW bit, RSTN bit and MCLK (Table 47).

Table 47. Power Off, Reset Function

[1] Power ON/OFF by MCLK Clock

The AK4493 detects a clock stop and all circuits except MCLK stop detection circuit, control register, bias generation circuit and LDO (only when the LDOE pin = “H”) stop operation if MCLK is not input for 1us (min.) during operation (PDN pin = “H”). In this case, the analog output goes floating state (Hi-Z). The AK4493 returns to normal operation if PW bit and RSTN bit are “1” after starting to supply MCLK again. The zero detect function is disabled when MCLK is stopped.

(5)

D/A Out (2) Hi-Z (Analog)

Notes:

(1)The AK4493 detects MCLK stop and becomes power off state when MCLK edge is not detected for 1us (min.) during operation.

(2)The analog output goes to floating state (Hi-Z).

(3)Click noise can be reduced by inputting “0” data when stopping and resuming MCLK supply.

(4)Resume MCLK input to release the power-off state by MCLK. In this case, power-up sequence by the PDN pin or PW bit is not necessary.

(5)The analog output corresponding to the digital input has group delay (GD).

Figure 62. Power ON/OFF by MCLK Clock

[AK4493]

[2] Power ON/OFF by PW bit

All circuits except control register, bias generation circuit and LDO (only when the LDOE pin = “H”) stop operation by setting PW bit to “0”. In this case, control register access is available. The analog output goes to floating state (Hi-Z). Figure 63 shows power ON/OFF sequence by PW bit.

Note:

(1)The analog output corresponding to the digital input has group delay (GD).

(2)The analog output is floating (Hi-Z) state when PW bit = “0”.

(3)Click noise occurs on an edge of PW bit. This noise is output even if “0” data is input.

(4)The zero detect function is enable when the AK4493 is power off (PW bit = “0”). This figure shows the seuqnece when DZFE bit = “1”, DZFB bit = “0” and DZFM bit = “0”.

(5)It takes 4~5/fs until a power down instruction is valid when writing PW bit and it takes 1~2/fs when releasing the power down.

(6)Mute the analog output externally if click noise (3) or Hi-z output (2) adversely affect system performance.

Figure 63. Power ON/OFF Timing Example

[AK4493]

[3] Reset by RSTN bit

Digital circuits except control registers and clock divider are reset by setting RSTN bit to “0”. In this case, control register settings are held, the analog output becomes VCML/R voltage and the DZFL/R pin outputs “H”. Figure 64 shows power ON/OFF sequence by RSTN bit.

Notes:

(1)The analog output corresponding to the digital input has group delay (GD).

(2)The analog output is VCML/R voltage when RSTN bit = “0”.

(3)Click noise occurs on an edge of internal RSTN signal. This noise is output even if “0” data is input.

(4)This figure shows the seuqnece when DZFE bit= “1”, DZFB bit = “0” and DZFM bit = “0”. The DZFL/R pin goes “H” on a falling edge of RSTN bit and goes “L” 2/fs after a rising edge of internal RSTN bit.

(5)It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes 2~3/fs when changing RSTN bit to “1”.

(6)Mute the analog output externally if click noise (3) adversely affect system performance.

Figure 64. Reset Timing Example