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DG408, DG409


Data Sheet	June 1999	File Number 3283.5

Single 8-Channel/Differential 4-Channel,

CMOS Analog Multiplexers

The DG408 Single 8-Channel, and DG409 Differential 4-Channel monolithic CMOS analog multiplexers are drop-in replacements for the popular DG508A and DG509A series devices. They each include an array of eight analog switches, a TTL/CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds and an ENABLE input for device selection when several multiplexers are present.

The DG408 and DG409 feature lower signal ON resistance

(<100Ω ) and faster switch transition time (tTRANS < 250ns) compared to the DG508A or DG509A. Charge injection has

been reduced, simplifying sample and hold applications. The improvements in the DG408 series are made possible by using a high-voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. Power supplies may be single-ended from +5V to +34V, or split from ± 5V to ± 20V.

The analog switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ± 5V analog input range.

Ordering Information

PART	TEMP. RANGE
NUMBER	(oC)	PACKAGE	PKG. NO.
DG408DJ	-40 to 85	16 Ld PDIP	E16.3

DG408DY	-40 to 85	16 Ld SOIC	M16.15

DG409DJ	-40 to 85	16 Ld PDIP	E16.3

DG409DY	-40 to 85	16 Ld SOIC	M16.15

Features

•ON Resistance (Max, 25oC). . . . . . . . . . . . . . . . . . . 100Ω

•Low Power Consumption (PD) . . . . . . . . . . . . . . . <11mW

•Fast Switching Action

-tTRANS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <250ns

-tON/OFF(EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . <150ns

•Low Charge Injection

•Upgrade from DG508A/DG509A

•TTL, CMOS Compatible

•Single or Split Supply Operation

Applications

•Data Acquisition Systems

•Audio Switching Systems

•Automatic Testers

•Hi-Rel Systems

•Sample and Hold Circuits

•Communication Systems

•Analog Selector Switch

Pinouts

DG408 (PDIP, SOIC)

TOP VIEW

A0	1	16	A1
EN			A2
EN	2	15	A2
V-			GND
V-	3	14	GND
S1			V+
S1	4	13	V+
S2			S5
S2	5	12	S5
S3			S6
S3	6	11	S6
S4			S7
S4	7	10	S7
D			S8
D	8	9	S8

DG409 (PDIP, SOIC)

TOP VIEW

A0	1	16	A1
EN			GND
EN	2	15	GND
V-			V+
V-	3	14	V+
S1A			S1B
S1A	4	13	S1B
S2A			S2B
S2A	5	12	S2B
S3A			S3B
S3A	6	11	S3B
S4A			S4B
S4A	7	10	S4B
DA			DB
DA	8	9	DB

1	CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
	1-888-INTERSIL or 321-724-7143 \| Copyright © Intersil Corporation 2000

DG408, DG409

Functional Block Diagrams

DG408

REF

†DIGITALINPUT PROTECTION

DECODER/

DRIVER

LEVEL

SHIFT

†

DG409

S1A

S4A

S1B

S4B

REF

†DIGITALINPUT PROTECTION

DECODER/

DRIVER

LEVEL

SHIFT

†

A0 A1 A2 EN

A0 A1

TRUTH TABLE DG408

A2	A1	A0	EN	ON SWITCH
X	X	X	0	NONE

0	0	0	1	1

0	0	1	1	2

0	1	0	1	3

0	1	1	1	4

1	0	0	1	5

1	0	1	1	6

1	1	0	1	7

1	1	1	1	8

TRUTH TABLE DG409

A1	A0	EN	ON SWITCH
X	X	0	NONE

0	0	1	1

0	1	1	2

1	0	1	3

1	1	1	4

NOTES:

1.VAH Logic “1”≥ 2.4V.

2.VAL Logic “0”≤ 0.8V.

DG408, DG409

Pin Descriptions - (DG408)

PIN	SYMBOL	DESCRIPTION

1	A0	Logic Decode Input (Bit 0, LSB)
2	EN	Enable Input

3	V-	Negative Power Supply Terminal

4	S1	Source (Input) for Channel 1
5	S2	Source (Input) for Channel 2
6	S3	Source (Input) for Channel 3
7	S4	Source (Input) for Channel 4
8	D	Drain (Output)

9	S8	Source (Input) for Channel 8
10	S7	Source (Input) for Channel 7
11	S6	Source (Input) for Channel 6
12	S5	Source (Input) for Channel 5
13	V+	Positive Power Supply Terminal (Substrate)

14	GND	Ground Terminal (Logic Common)

15	A2	Logic Decode Input (Bit 2, MSB)
16	A1	Logic Decode Input (Bit 1)

Pin Descriptions - (DG409)

PIN	SYMBOL	DESCRIPTION

1	A0	Logic Decode Input (Bit 0, LSB)
2	EN	Enable Input

3	V-	Negative Power Supply Terminal

4	S1A	Source (Input) for Channel 1a
5	S2A	Source (Input) for Channel 2a
6	S3A	Source (Input) for Channel 3a
7	S4A	Source (Input) for Channel 4a
8	DA	Drain a (Output a)
9	DB	Drain b (Output b)
10	S4B	Source (Input) for Channel 4b
11	S3B	Source (Input) for Channel 3b
12	S2B	Source (Input) for Channel 2b
13	S1B	Source (Input) for Channel 1b
14	V+	Positive Power Supply Terminal

15	GND	Ground Terminal (Logic Common)

16	A1	Logic Decode Input (Bit 1, MSB)

DG408, DG409

Absolute Maximum Ratings

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V Digital Inputs, VS, VD (Note 3). . . . . .(V-) -2V to (V+) + 2V or 20mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA

Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA

Thermal Information
Thermal Resistance (Typical, Note 4)	θ JA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 110
Maximum Junction Temperature . . . . . . . . . . . . . . . .	. . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 125oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . . .300oC
(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTES:

3.Signals on SX, DX, EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.

4.θ JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Speciﬁcations Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified

				TEMP (oC)	(NOTE 5)	(NOTE 6)	(NOTE 5)
	PARAMETER	TEST CONDITIONS		TEMP (oC)	MIN	TYP	MAX	UNITS
DYNAMIC CHARACTERISTICS

Transition Time, tTRANS		(See Figure 1)		Full	-	160	250	ns
Break-Before-Make Interval, tOPEN		(See Figure 3)		25	10	-	-	ns
Enable Turn-ON Time, tON(EN)		(See Figure 2)		25	-	115	150	ns
				Full	-	-	225	ns

Enable Turn-OFF Time, tOFF(EN)		(See Figure 2)		Full	-	105	150	ns
Charge Injection, Q		CL = 10nF, VS = 0V		25	-	20	-	pC
OFF Isolation		VEN = 0V, RL = 1kΩ ,		25	-	-75	-	dB
		f = 100kHz (Note 9)

Logic Input Capacitance, CIN		f = 1MHz		25	-	8	-	pF
Source OFF Capacitance, CS(OFF)		VEN = 0V, VS = 0V,		25	-	3	-	pF
		f = 1MHz

Drain OFF Capacitance, CD(OFF)		VEN = 0V, VD = 0V,
	DG408	f = 1MHz		25	-	26	-	pF

	DG409			25	-	14	-	pF

Drain ON Capacitance, CD(ON)		VEN = 3V, VD = 0V,
	DG408	f = 1MHz, VA = 0V or 3V		25	-	37	-	pF
	DG409			25	-	25	-	pF

DIGITAL INPUT CHARACTERISTICS

Logic Input Current,		VA = 2.4V, 15V		Full	-10	-	10	µ	A
Input Voltage High, IAH
Logic Input Current,		VEN = 0V, 2.4V,		Full	-10	-	10	µ	A
Input Voltage Low, IAL		VA = 0V
ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG				Full	-15	-	15	V
Drain-Source ON Resistance,		VD = ± 10V, IS = -10mA		25	-	40	100	Ω
rDS(ON)		(Note 7)
rDS(ON)		(Note 7)		Full	-	-	125	Ω
rDS(ON) Matching Between Channels,		VD = 10V, -10V (Note 8)		25	-	-	15	Ω
∆ rDS(ON)
Source OFF Leakage Current, IS(OFF)		VEN = 0V, VS = ± 10V,		25	-0.5	-	0.5	nA
		VD =	+10V
		VD =	+10V	Full	-5	-	5	nA

DG408, DG409

Electrical Speciﬁcations		Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified (Continued)
					TEMP (oC)		(NOTE 5)		(NOTE 6)		(NOTE 5)
	PARAMETER		TEST CONDITIONS		TEMP (oC)		MIN		TYP		MAX	UNITS
Drain OFF Leakage Current, ID(OFF)			VEN = 0V, VD = ± 10V,
	DG408		VS =	+10V	25		-1	-		1		nA
						Full	-20	-		20		nA

	DG409				25		-1	-		1		nA

						Full	-10	-		10		nA

Drain ON Leakage Current, ID(ON)			VS = VD = ± 10V (Note 7)
	DG408				25		-1	-		1		nA

						Full	-20	-		20		nA

	DG409				25		-1	-		1		nA

						Full	-10	-		10		nA

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+			VEN = 0V, VA = 0V (Standby)			Full	-	10		75		µ A
Negative Supply Current, I-						Full	-75	1		-		µ A

Positive Supply Current, I+			VEN = 2.4V, VA = 0V		25		-	0.2		0.5		mA
			(Enabled)
			(Enabled)			Full	-	-		2		mA
						Full	-	-		2		mA

Negative Supply Current, I-						Full	-500	-		-		µ A

Electrical Speciﬁcations		Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V,
		Unless Otherwise Speciﬁed

				TEST		TEMP (oC)	(NOTE 5)		(NOTE 6)		(NOTE 5)
	PARAMETER			CONDITION		TEMP (oC)	MIN		TYP		MAX	UNITS
DYNAMIC CHARACTERISTICS

Switching Time of Multiplexer, tTRANS			VS1 = 8V, VS8 = 0V, VIN = 2.4V			25	-		180		-	ns
Enable Turn-ON Time, tON(EN)			VINH = 2.4V, VINL = 0V,			25	-		180		-	ns
			VS1 = 5V
Enable Turn-OFF Time, tOFF(EN)			VS1 = 5V			25	-		120		-	ns
Enable Turn-OFF Time, tOFF(EN)						25	-		120		-	ns
Charge Injection, Q			CL = 10nF, VGEN = 0V,			25	-		5		-	pC
			RGEN = 0Ω
ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG						Full	0		-		12	V
Drain-Source ON-Resistance,			VD = 3V, 10V, IS = -1mA			25	-		90		-	Ω
rDS(ON)			(Note 7)

NOTES:

5.The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6.Typical values are for DESIGN AID ONLY, not guaranteed nor production tested.

7.Sequence each switch ON.

8.∆ rDS(ON) = rDS(ON) (Max) - rDS(ON) (Min).

9.Worst case isolation occurs on channel 4 due to proximity to the drain pin.

Test Circuits and Waveforms

			+15V
	+2.4V
	EN		V+	S1	± 10V
	EN			S1
LOGIC	A0		S2 - S7
LOGIC	A1	DG408		S8	±10V
INPUT	A1	DG408		S8	±10V
INPUT	A2 GND			D
	A2 GND		V-	D
	50Ω				300Ω
			-15V

FIGURE 1A. DG408 TEST CIRCUIT

DG408, DG409

	SWITCH	LOGIC
	OUTPUT	LOGIC
	OUTPUT	INPUT
	VO	INPUT
	VO
	35pF

+15V

+2.4V
EN		V+	S1B	± 10V
EN			S1B
	S1A - S4A, DA
A0	DG409 S4B			±10V
A1	GND V-		DB
50Ω				300Ω
		-15V

SWITCH OUTPUT VO

35pF

FIGURE 1B. DG409 TEST CIRCUIT

				tr < 20ns
	3V			tf < 20ns
LOGIC	3V
LOGIC		50%		50%
INPUT	0V	50%		50%
INPUT

	S1	ON
SWITCH	VS1			0.8 VS1
OUTPUT	0V
VO	VS8		0.8 VS8
	VS8
	tTRANS			tTRANS
			S8	ON

FIGURE 1C. MEASUREMENT POINTS

FIGURE 1. TRANSITION TIME

+15V

V+ S1

-5V

V+S1B

-5V

DG408

DG409

LOGIC

S2 - S8

SWITCH

S1A - S4A

SWITCH

LOGIC

INPUT

OUTPUT

2B -

4B,

OUTPUT

VIN

V- D

INPUT VIN

EN GND

V-

50Ω

300Ω

35pF

50Ω

300Ω

35pF

-15V

FIGURE 2A. DG408 TEST CIRCUIT

FIGURE 2B. DG409 TEST CIRCUIT

tr < 20ns

LOGIC

tf < 20ns

50%

INPUT

VIN

tON(EN)

SWITCH

OUTPUT

0.9 VO

tOFF(EN)

FIGURE 2C. MEASUREMENT POINTS

FIGURE 2. ENABLE SWITCHING TIMES

DG408, DG409

Test Circuits and Waveforms (Continued)

			+15V					tr < 20ns
	+2.4V					LOGIC	3V	tf < 20ns
			V+			INPUT	0V
			V+	+5V (VS)			0V
	EN ALL S AND DA			+5V (VS)			VS
LOGIC	A0	DG408			SWITCH	SWITCH	VS
	A1	DG409			SWITCH		80%	80%
					OUTPUT
INPUT					OUTPUT
INPUT	A2 GND V- D, DB				VO	OUTPUT
	A2 GND V- D, DB				VO	VO
	50Ω			300Ω	35pF		0V
			-15V				tOPEN
			-15V
	FIGURE 3A. TEST CIRCUIT						FIGURE 3B. MEASUREMENT POINTS
				FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
			+15V
						LOGIC	3V
						LOGIC
	RGEN			V+		INPUT	0V
		SX		D	VO
V	CHANNEL	A	0		CL
GEN	CHANNEL		0		10nF	SWITCH
	SELECT	A1			10nF	SWITCH		∆ VO
	SELECT	A2				OUTPUT	ON	∆ VO
		A2				OUTPUT	ON	OFF
		EN GND		V-
							∆ VO IS THE MEASURED VOLTAGE DUE
							TO CHARGE TRANSFER ERROR, Q
	LOGIC INPUT		-15V				Q = CL x ∆ VO
	FIGURE 4A. TEST CIRCUIT						FIGURE 4B. MEASUREMENT POINTS

FIGURE 4. CHARGE INJECTION

		0V	+15V					5V	+15V
		0V	+15V
	VIN						S1	EN	V+
	SX	EN	V+				S1	EN	V+
	SX	EN	V+		1kΩ	VIN	SX
	\|					VIN	SX
	\|			VO			\|
	\|			VO			\|			VO
	\|		D				\|			VO
	S8		D				S8			D
	S8						S8			D
	A2			1kΩ			A2			1kΩ
SIGNAL	A1						A1			1kΩ
SIGNAL	A1				SIGNAL		A1
GENERATOR	A0		V-		SIGNAL		A0
	A0				GENERATOR				V-
					GENERATOR

		GND						GND
			-15V					GND
			-15V						-15V
									-15V
ANALYZER					ANALYZER
					ANALYZER
			VOUT						V	OUT
	OFF ISOLATION = 20 Log -----------------									OUT
			V	IN			CROSSTALK = 20 Log -----------------
				IN					VIN

FIGURE 5. OFF ISOLATION

FIGURE 6. CROSSTALK

DG408, DG409

Test Circuits and Waveforms (Continued)

	5V	+15V		3V OR 0V	+15V
	VIN
	S1 EN	V+		EN	V+
			VO	A2	S1
			VO		\|
		D	CHANNEL	A1	\|
SIGNAL	A2		SELECT	A1	S8
SIGNAL	A2		RL		IMPEDANCE
GENERATOR	A1		RL		IMPEDANCE
GENERATOR	A1			A0	ANALYZER
	A0			A0	D
	A0	V-			D
		V-			V-
	GND			GND
		-15V			-15V

ANALYZER

VOUT
INSERTION LOSS = 20 Log -----------------
VIN
FIGURE 7. INSERTION LOSS	FIGURE 8. SOURCE/DRAIN CAPACITANCES

Typical Applications

Overvoltage Protection

A very convenient form of overvoltage protection consists of adding two small signal diodes (1N4148, 1N914 type) in series with the supply pins (see Figure 9). This arrangement effectively blocks the ﬂow of reverse currents. It also ﬂoats the supply pin above or below the normal V+ or V- value. In this case the overvoltage signal actually becomes the power supply of the IC. From the point of view of the chip, nothing has changed, as long as the difference V+ - (V-) doesn’t exceed 44V. The addition of these diodes will reduce the analog signal range to 1V below V+ and 1V above V-, but it preserves the low channel resistance and low leakage characteristics.

Typical application information is for Design Aid Only, not guaranteed and not subject to production testing.

V+

1N4148

DG408

1N4148

V-

FIGURE 9. OVERVOLTAGE PROTECTION USING BLOCKING DIODES

				DG408, DG409
Typical Performance Curves
	3.5				75
	3.0						CD(ON)
		V+ = +15V					CD(ON)
		V- = -15V
	2.0				50
(pA)				(pF)			CD(OFF)
(pA)				D

IN	1.0			S,
I	1.0			C
	0.5pA				25
	0.0						CS(OFF)
							CS(OFF)
	-1.0				0	4	8	12
	0	5	10	15	0	4	8	12
			VIN (V)				VA (V)

FIGURE 10. INPUT LOGIC CURRENT vs LOGIC INPUT VOLTAGE

	80
		V+ = +15V
		V- = -15V
	60	CD(ON)
		CD(ON)
(pF)	40	CD(OFF)
D	40
S,
C
	20	CS(OFF)
		CS(OFF)
	0
	-15	0	15

VA (V)

FIGURE 12. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE

FIGURE 11. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE (SINGLE 12V SUPPLY)

VSUPPLY = ± 15V

VIN = 0V

-200

IIN (pA)

-400

-600

-800

-55

125

TEMPERATURE (oC)

FIGURE 13. LOGIC INPUT CURRENT vs TEMPERATURE

	60
	40	DG408 ID(OFF)
	40	DG409 ID(OFF)
		DG409 ID(OFF)
	20	DG409 ID(ON)
	20	DG408 ID(ON)
		DG408 ID(ON)
(pA)	0
D	0
D
I
	-20
	-40	VS = 0V FOR ID(OFF)
		VS = VD FOR ID(ON)

-60

VD (V)

FIGURE 14. DRAIN LEAKAGE CURRENT vs SOURCE/DRAIN VOLTAGE (SINGLE 12V SUPPLY)

	100
		V+ = 15V
	60	V- = -15V
	60	VS = -VD FOR ID(OFF)
		VS = -VD FOR ID(OFF)
		VD = VS(OPEN) FOR ID(ON)
	20
(pA)	-20
D
I
	-60
		DG409 ID(OFF)
	-100	DG409 ID(ON)
		DG408 ID(ON), ID(OFF)
	-140
	-15	0	15
		VS, VD (V)

FIGURE 15. DRAIN LEAKAGE CURRENT vs SOURCE/DRAIN VOLTAGE

			DG408, DG409
Typical Performance Curves			(Continued)
	20			2.0
	15
				1.5
	10	V+ = +15V
	10	V- = -15V
(pA)		V- = -15V
(pA)			(V)	1.0
S(OFF)	5		V
	5		IN
I
	0		V+ = +12V
			V+ = +12V	0.5
			V- = 0V	0.5
			V- = 0V
	-5
	-10			0.0
	-15	0	15	4	8	12	16	20
		VS (V)				VSUPPLY (± V)

FIGURE 16. SOURCE LEAKAGE CURRENT vs SOURCE VOLTAGE

	105
		VSUPPLY = ± 15V
	104
	103			EN = 2.4V
	103
) ( A)	102
-(I-				EN = 0V
	10			EN = 0V
	10
	1
	0.1
	100	1K	10K	100K	1M	10M
		SWITCHING FREQUENCY (Hz)

FIGURE 18. NEGATIVE SUPPLY CURRENT vs SWITCHING

		FREQUENCY
	105			VSUPPLY = ± 15V
				VSUPPLY = ± 15V
	104	I+
-II+,(nA)	103
-II+,(nA)	10
	102
	1
	0.1	-(I-)
		-(I-)
	0.01
	-55	5	45	85	125
		TEMPERATURE (oC)

FIGURE 20. ISUPPLY vs TEMPERATURE

FIGURE 17. INPUT SWITCHING THRESHOLD vs SUPPLY VOLTAGE

	104
	104
		VSUPPLY = ± 15V
	103
	103
(mA)	102
	102
	10
	10
I+
	1
			EN = 2.4V
			EN = 2.4V
	0.1

					EN = 0V
					EN = 0V
	0.01


	100	1K	10K	100K		1M	10M
		SWITCHING FREQUENCY (Hz)

FIGURE 19. POSITIVE SUPPLY CURRENT vs SWITCHING FREQUENCY

0
-200
-I (nA)
-400
	V+ = 15V
	V- = -15V
-600	VIN = 0V
	VEN = 0V
-800
-55	5	45	85	125
	TEMPERATURE (oC)

FIGURE 21. NEGATIVE SUPPLY CURRENT vs TEMPERATURE

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A0	1	16	A1
EN			A2
EN	2	15	A2
V-			GND
V-	3	14	GND
S1			V+
S1	4	13	V+
S2			S5
S2	5	12	S5
S3			S6
S3	6	11	S6
S4			S7
S4	7	10	S7
D			S8
D	8	9	S8

A0	1	16	A1
EN			GND
EN	2	15	GND
V-			V+
V-	3	14	V+
S1A			S1B
S1A	4	13	S1B
S2A			S2B
S2A	5	12	S2B
S3A			S3B
S3A	6	11	S3B
S4A			S4B
S4A	7	10	S4B
DA			DB
DA	8	9	DB

A0	1	16	A1
EN			A2
EN	2	15	A2
V-			GND
V-	3	14	GND
S1			V+
S1	4	13	V+
S2			S5
S2	5	12	S5
S3			S6
S3	6	11	S6
S4			S7
S4	7	10	S7
D			S8
D	8	9	S8

A0	1	16	A1
EN			GND
EN	2	15	GND
V-			V+
V-	3	14	V+
S1A			S1B
S1A	4	13	S1B
S2A			S2B
S2A	5	12	S2B
S3A			S3B
S3A	6	11	S3B
S4A			S4B
S4A	7	10	S4B
DA			DB
DA	8	9	DB

A0	1	16	A1
EN			A2
EN	2	15	A2
V-			GND
V-	3	14	GND
S1			V+
S1	4	13	V+
S2			S5
S2	5	12	S5
S3			S6
S3	6	11	S6
S4			S7
S4	7	10	S7
D			S8
D	8	9	S8

A0	1	16	A1
EN			GND
EN	2	15	GND
V-			V+
V-	3	14	V+
S1A			S1B
S1A	4	13	S1B
S2A			S2B
S2A	5	12	S2B
S3A			S3B
S3A	6	11	S3B
S4A			S4B
S4A	7	10	S4B
DA			DB
DA	8	9	DB