Philips Semiconductors Product specification
PowerMOS transistor |
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BUK107-50DS |
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Logic level TOPFET |
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DESCRIPTION |
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QUICK REFERENCE DATA |
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Monolithic overload protected logic |
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PARAMETER |
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MAX. |
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UNIT |
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level power MOSFET in a surface |
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mount plastic envelope, intended as |
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VDS |
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Continuous drain source voltage |
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50 |
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V |
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a general purpose switch for |
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automotive systems and other |
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Continuous drain current |
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0.5 |
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A |
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applications. |
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PD |
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Total power dissipation |
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1.8 |
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W |
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APPLICATIONS |
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Tj |
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Continuous junction temperature |
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150 |
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˚C |
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General controller for driving |
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mΩ |
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lamps |
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RDS(ON) |
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Drain-source on-state resistance |
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175 |
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small motors |
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solenoids |
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FEATURES |
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FUNCTIONAL BLOCK DIAGRAM |
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Vertical power DMOS output |
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stage |
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DRAIN |
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Overload protection by current |
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limiting and overtemperature |
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sensing |
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Latched overload protection |
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O/V |
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reset by input |
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CLAMP |
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Input clamping suitable for |
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POWER |
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pull-up resistor drive circuit |
INPUT |
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MOSFET |
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Control of power MOSFET |
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RIG |
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and supply of overload |
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protection circuits |
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derived from input |
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LOGIC AND |
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ESD protection on all pins |
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PROTECTION |
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Overvoltage clamping for turn |
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off of inductive loads |
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SOURCE |
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Fig.1. Elements of the TOPFET. |
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PINNING - SOT223 |
PIN CONFIGURATION |
SYMBOL |
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PIN |
DESCRIPTION |
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4 |
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D |
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TOPFET |
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1 |
input |
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2 |
drain |
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I |
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P |
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3 |
source |
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4 |
drain (tab) |
1 |
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3 |
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September 1994 |
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1 |
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Rev 1.000 |
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Philips Semiconductors Product specification
PowerMOS transistor |
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BUK107-50DS |
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Logic level TOPFET |
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LIMITING VALUES |
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Limiting values in accordance with the Absolute Maximum System (IEC 134) |
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SYMBOL |
PARAMETER |
CONDITIONS |
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MIN. |
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MAX. |
UNIT |
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V |
Continuous drain source voltage1 |
- |
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50 |
V |
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DS |
Continuous drain current2 |
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I |
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self limiting |
A |
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D |
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II |
Continuous input current |
clamping |
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mA |
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IIRM |
Non-repetitive peak input current |
tp ≤ 1 ms |
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10 |
mA |
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PD |
Total power dissipation |
Tamb = 25 ˚C |
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1.8 |
W |
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Tstg |
Storage temperature |
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-55 |
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150 |
˚C |
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T |
Continuous junction temperature |
normal operation3 |
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150 |
˚C |
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j |
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ESD LIMITING VALUE |
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SYMBOL |
PARAMETER |
CONDITIONS |
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MIN. |
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MAX. |
UNIT |
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VC |
Electrostatic discharge capacitor |
Human body model; |
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kV |
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voltage |
C = 250 pF; R = 1.5 kΩ |
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OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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EDSM |
Non-repetitive clamping energy |
Tb ≤ 25 |
˚C; IDM < ID(lim); |
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100 |
mJ |
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inductive load |
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EDRM |
Repetitive clamping energy |
Tb ≤ 75 |
˚C; IDM = 50 mA; |
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4 |
mJ |
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f = 250 Hz |
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OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads. Overload protection operates by means of drain current limiting and activating the overtemperature protection.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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V |
Protection supply voltage4 |
for valid protection |
6 |
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V |
ISP |
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VDDP |
Protected drain source supply voltage |
II = 1.5 mA |
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35 |
V |
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off to protect itself when there is an overload fault condition.
It remains latched off until reset by the input.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Overload protection |
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ID(lim) |
Drain current limiting |
II = 1.5 mA |
0.5 |
1 |
1.5 |
A |
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Overtemperature protection |
only in drain current limiting |
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Tj(TO) |
Threshold junction temperature |
II = 1.5 mA |
100 |
130 |
160 |
˚C |
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Not in an overload condition with drain current limiting.
4 The input voltage for which the overload protection circuits are functional.
September 1994 |
2 |
Rev 1.000 |
Philips Semiconductors Product specification
PowerMOS transistor |
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BUK107-50DS |
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Logic level TOPFET |
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THERMAL CHARACTERISTICS |
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Thermal resistance |
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R |
Junction to board1 |
Mounted on any PCB |
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40 |
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K/W |
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th j-b |
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Rth j-a |
Junction to ambient |
Mounted on PCB of fig. 19 |
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70 |
K/W |
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STATIC CHARACTERISTICS |
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Tb = 25 ˚C unless otherwise specified |
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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V(CL)DSS |
Drain-source clamping voltage |
VIS = 0 V; ID = 10 mA |
50 |
55 |
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V |
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V(CL)DSS |
Drain-source clamping voltage |
VIS = 0 V; IDM = 200 mA; |
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56 |
70 |
V |
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tp ≤ 300 μs; δ ≤ 0.01 |
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μA |
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IDSS |
Off-state drain current |
VDS = 45 V; VIS = 0 V |
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0.5 |
2 |
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IDSS |
Off-state drain current |
VDS = 50 V; VIS = 0 V |
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1 |
20 |
μA |
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IDSS |
Off-state drain current |
VDS = 40 V; VIS = 0 V; Tj = 100 ˚C |
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10 |
100 |
μA |
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RDS(ON) |
Drain-source on-state |
II |
= 1.5 mA; IDM = 100 mA; |
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125 |
175 |
mΩ |
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resistance2 |
t |
≤ 300 μs; δ ≤ 0.01 |
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p |
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INPUT CHARACTERISTICS
Tb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input. The input clamping is suitable for a drive circuit with a pull-up resistor.
SYMBOL |
PARAMETER |
CONDITIONS |
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MIN. |
TYP. |
MAX. |
UNIT |
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VIS(TO) |
Input threshold voltage |
VDS = 5 V; ID = 1 mA |
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1.7 |
2.2 |
2.7 |
V |
IIS |
Input supply current |
normal operation; |
VIS = 6 V |
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550 |
750 |
μA |
IISL |
Input supply current |
protection latched; |
VIS = 5 V |
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500 |
650 |
μA |
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Protection latch reset voltage3 |
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VIS = 3.5 V |
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250 |
400 |
μA |
V |
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1 |
2.2 |
3.5 |
V |
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ISR |
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V(CL)IS |
Input clamping voltage |
II = 1.5 mA |
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6 |
7.5 |
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V |
RIG |
Input series resistance |
to gate of power MOSFET |
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33 |
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kΩ |
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SWITCHING CHARACTERISTICS
Tamb = 25 ˚C; resistive load RL = 50 Ω; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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td on |
Turn-on delay time |
VIS = 0 V to II = 1.5 mA |
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4 |
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μs |
tr |
Rise time |
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16 |
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μs |
td off |
Turn-off delay time |
II = 1.5 mA to VIS = 0 V |
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3 |
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μs |
tf |
Fall time |
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6 |
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μs |
1 Temperature measured 1.3 mm from tab.
2 Continuous input voltage. The specified pulse width is for the drain current.
3 The input voltage below which the overload protection circuits will be reset.
September 1994 |
3 |
Rev 1.000 |
Philips Semiconductors |
Product specification |
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PowerMOS transistor |
BUK107-50DS |
Logic level TOPFET |
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120 |
PD% |
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Normalised Power Derating |
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110 |
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100 |
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90 |
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80 |
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70 |
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60 |
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50 |
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40 |
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30 |
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20 |
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10 |
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0 |
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40 |
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80 |
100 |
120 |
140 |
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Tmb / |
C |
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Fig.2. Normalised limiting power dissipation. |
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PD% = 100×PD/PD(25 ˚C) = f(Tmb) |
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ID / A |
BUK107-50DS |
2.0
CURRENT LIMITING OCCURS
WITHIN THE SHADED REGION
1.5 |
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1.0 |
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TYP. |
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0.5 |
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0 |
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0 |
20 |
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80 |
100 |
120 |
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140 |
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Tamb / C |
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Fig.3. |
Continuous drain current. |
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ID = f(Tamb); condition: II = 1.5 mA |
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ID / A |
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1.5 |
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VIS / V = |
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1 |
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7 |
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6 |
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5 |
0.5 |
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0 |
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0 |
4 |
8 |
12 |
16 |
20 |
24 |
28 |
32 |
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VDS / V |
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Fig.4. Typical on-state characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VIS; tp = 300 ms
a |
Normalised RDS(ON) = f(Tj) |
1.5 |
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1.0 |
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0.5 |
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0 |
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-60 |
-40 -20 |
0 |
20 |
40 |
60 |
80 100 120 140 |
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Tj / |
C |
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Fig.5. Normalised drain-source on-state resistance. |
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a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 100 mA; II = 1.5 mA |
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RDS(ON) / mOhm |
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BUK107-50DS |
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240 |
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200 |
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160 |
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TYP. |
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120 |
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80 |
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40 |
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0 |
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0 |
2 |
4 |
6 |
8 |
10 |
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VIS / V |
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Fig.6. |
Typical on-state resistance, Tj = 25 ˚C. |
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RDS(ON) = f(VIS); conditions: ID = 100 mA, tp = 300 ms |
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ID / A |
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1.5 |
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1 |
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0.5 |
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0 |
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0 |
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4 |
6 |
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10 |
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VIS / V |
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Fig.7. |
Typical transfer characteristics, Tj |
= 25 ˚C. |
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ID = f(VIS); conditions: VDS = 10 V, tp = 300 ms |
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September 1994 |
4 |
Rev 1.000 |
Philips Semiconductors |
Product specification |
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PowerMOS transistor |
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BUK107-50DS |
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Logic level TOPFET |
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Tj(TO) / C |
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BUK107-50DS |
VIS(TO) / V |
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BUK107-50DS |
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200 |
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180 |
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3 |
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160 |
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MAX. |
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140 |
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TYP. |
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TYP. |
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2 |
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120 |
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MIN. |
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100 |
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80 |
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1 |
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60 |
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0 |
2 |
4 |
6 |
8 |
10 |
-50 |
0 |
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100 |
150 |
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VIS / V |
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Tj / C |
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Fig.8. |
Typical overtemperature protection threshold. |
Fig.11. |
Input threshold voltage. |
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Tj(TO) = f(VIS); condition: VDS = 10 V |
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VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V |
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IIS & IISL / mA |
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BUK107-50DS |
II / mA |
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BUK107-50DS |
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1.0 |
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10 |
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0.9 |
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9 |
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0.8 |
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8 |
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0.7 |
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LATCHED |
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7 |
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0.6 |
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6 |
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0.5 |
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5 |
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0.4 |
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IISL |
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NORMAL |
4 |
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0.3 |
RESET |
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3 |
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IIS |
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0.2 |
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2 |
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0.1 |
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1 |
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0 |
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0 |
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0 |
2 |
4 |
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6 |
8 |
0 |
2 |
4 |
6 |
8 |
10 |
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VIS / V |
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VIS / V |
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Fig.9. |
Typical DC input characteristics, Tj |
= 25 ˚C. |
Fig.12. |
Typical input clamping characteristic. |
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IIS & IISL = f(VIS); normal operation & protection latched |
II = f(VIS); normal operation, Tj = 25 ˚C. |
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IIS / uA |
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BUK107-50DS |
ID / mA |
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BUK107-50DS |
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500 |
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200 |
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VIS / V = |
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400 |
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150 |
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5 V |
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300 |
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TYP. |
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100 |
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200 |
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4 V |
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50 |
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100 |
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0 |
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0 |
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-50 |
0 |
50 |
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100 |
150 |
50 |
52 |
54 |
56 |
58 |
60 |
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Tj / C |
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VDS / V |
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Fig.10. Typical DC input current. |
Fig.13. Overvoltage clamping characteristic, 25 ˚C. |
IIS = f(Tj); parameter VIS; normal operation |
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 300 μs |
September 1994 |
5 |
Rev 1.000 |
Philips Semiconductors |
Product specification |
|
|
PowerMOS transistor |
BUK107-50DS |
Logic level TOPFET |
|
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VDD |
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RI |
RL |
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VIS |
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VDS |
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D |
measure |
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TOPFET |
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10 kO |
I |
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D.U.T. |
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P |
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BC337 |
S |
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0V
Fig.14. Test circuit for resistive load switching times. Select RI to give II = 1.5 mA, ie 3.3 kΩ approx.
VIS & VDS / V |
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BUK107-50DS |
||
15 |
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10 |
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VDS |
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VIS |
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5 |
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0 |
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-10 |
10 |
30 |
50 |
70 |
90 |
time / us
Fig.15. Typical switching waveforms, resistive load . RL = 50 Ω; adjust VDD to obtain ID = 250 mA; Tj = 25˚C
IDSS |
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BUK107-50DS |
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10 uA |
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1 uA |
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100 nA |
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10 nA |
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-50 |
0 |
50 |
100 |
150 |
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Tj / C |
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Fig.16. Typical drain source leakage current IDSS = f(Tj); conditions: VDS = 40 V; VIS = 0 V.
1E+02 |
Zth j-amb / (K/W) |
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BUK107-50DS |
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D = |
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0.5 |
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1E+01 |
0.2 |
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0.1 |
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0.05 |
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1E+00 |
0.02 |
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tp |
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P |
tp |
D = |
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D |
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T |
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1E-01 |
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T |
t |
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0 |
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1E-02 |
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1E-07 |
1E-05 |
1E-03 |
1E-01 |
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1E+01 |
1E+03 |
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t / s |
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Fig.17. Transient thermal impedance, TOPFET mounted on PCB of fig 19. Zth j-amb = f(t); parameter D = tp/T
September 1994 |
6 |
Rev 1.000 |
Philips Semiconductors Product specification
PowerMOS transistor |
BUK107-50DS |
Logic level TOPFET |
|
|
|
MOUNTING INSTRUCTIONS |
PRINTED CIRCUIT BOARD |
|
Dimensions in mm. |
Dimensions in mm. |
3.8 |
|
36 |
min |
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1.5 |
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18 |
min |
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60 |
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4.6 |
4.5 |
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9 |
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2.3 |
6.3 |
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1.5 |
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min |
10 |
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(3x) |
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1.5 |
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min |
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4.6 |
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7 |
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15 |
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50 |
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Fig.18. Soldering pattern for surface mounting. |
Fig.19. PCB for thermal resistance and power rating. |
|
PCB: FR4 epoxy glass (1.6 mm thick), |
|
copper laminate (35 μm thick). |
September 1994 |
7 |
Rev 1.000 |
Philips Semiconductors Product specification
PowerMOS transistor |
BUK107-50DS |
Logic level TOPFET |
|
|
|
MECHANICAL DATA |
|
Dimensions in mm
Net Mass: 0.11 g
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6.7 |
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6.3 |
B |
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0.32 |
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3.1 |
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0.2 |
M |
A |
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0.24 |
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2.9 |
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|||
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4 |
A |
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0.10 |
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0.02 |
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3.7 |
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7.3 |
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3.3 |
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6.7 |
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16 |
13 |
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max |
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10 |
1 |
2 |
3 |
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max |
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1.8 |
1.05 |
2.3 |
0.80 |
0.1 |
M |
B |
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max |
0.85 |
|
0.60 |
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|||
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(4x) |
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4.6 |
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Fig.20. SOT223 surface mounting package1.
1 For further information, refer to surface mounting instructions for SOT223 envelope.
September 1994 |
8 |
Rev 1.000 |
Philips Semiconductors |
Product specification |
|
|
PowerMOS transistor |
BUK107-50DS |
Logic level TOPFET |
|
|
|
DEFINITIONS
Data sheet status
Objective specification |
This data sheet contains target or goal specifications for product development. |
|
|
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification |
This data sheet contains final product specifications. |
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
September 1994 |
9 |
Rev 1.000 |