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Philips Semiconductors Product specification

PowerMOS transistor

BUK102-50DL

Logic level TOPFET

DESCRIPTION

QUICK REFERENCE DATA

Monolithic temperature and

SYMBOL

PARAMETER

MAX.

UNIT

overload protected logic level power

MOSFET in a 3 pin plastic

VDS

Continuous drain source voltage

envelope, intended as a general

Continuous drain current

purpose switch for automotive

Total power dissipation

125

systems and other applications.

Continuous junction temperature

150

˚C

APPLICATIONS

RDS(ON)

Drain-source on-state resistance

mΩ

IISL

Input supply current

VIS = 5 V

650

μA

General controller for driving

lamps

motors

solenoids

heaters

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Vertical power DMOS output
stage				DRAIN
Low on-state resistance
Overload protection against
over temperature
Overload protection against			O/V
short circuit load			O/V
short circuit load			CLAMP
Latched overload protection			CLAMP	POWER
reset by input		INPUT		POWER
reset by input		INPUT		MOSFET
5 V logic compatible input level			RIG	MOSFET
Control of power MOSFET
and supply of overload
protection circuits		LOGIC AND
derived from input		LOGIC AND
derived from input		PROTECTION
Lower operating input current		PROTECTION
permits direct drive by
micro-controller
ESD protection on input pin
Overvoltage clamping for turn				SOURCE
off of inductive loads				SOURCE
		Fig.1. Elements of the TOPFET.
PINNING - TO220AB		PIN CONFIGURATION	SYMBOL
PIN	DESCRIPTION	tab		D
		tab	TOPFET	D
1	input		TOPFET
1	input
2	drain		I
			I
			P
3	source
tab	drain	1 2 3		S
		1 2 3		S

April 1993

Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistor					BUK102-50DL
Logic level TOPFET

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL	PARAMETER	CONDITIONS		MIN.	MAX.	UNIT

V	Continuous drain source voltage1	-		-	50	V
DS
VIS	Continuous input voltage	-	≤ 25 ˚C; VIS = 5 V	0	6	V
ID	Continuous drain current	Tmb	≤ 25 ˚C; VIS = 5 V	-	45	A
ID	Continuous drain current	Tmb	≤ 100 ˚C; VIS = 5 V	-	28	A
IDRM	Repetitive peak on-state drain current	Tmb	≤ 25 ˚C; VIS = 5 V	-	180	A
PD	Total power dissipation	Tmb	≤ 25 ˚C	-	125	W
Tstg	Storage temperature	-		-55	150	˚C
T	Continuous junction temperature2	normal operation		-	150	˚C
j
Tsold	Lead temperature	during soldering		-	250	˚C

OVERLOAD PROTECTION LIMITING VALUES

With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.

SYMBOL	PARAMETER	CONDITIONS		MIN.	MAX.	UNIT

V	Protection supply voltage3	for valid protection		4	-	V
ISP
	Over temperature protection
VDDP(T)	Protected drain source supply voltage	VIS = 5	V	-	50	V
	Short circuit load protection4
V	Protected drain source supply voltage5	V = 5	V	-	16	V
DDP(P)		IS
PDSM	Instantaneous overload dissipation	Tmb = 25 ˚C		-	2.1	kW

OVERVOLTAGE CLAMPING LIMITING VALUES

At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.

SYMBOL	PARAMETER	CONDITIONS		MIN.	MAX.	UNIT

IDROM	Repetitive peak clamping current	VIS = 0 V		-	45	A
EDSM	Non-repetitive clamping energy	Tmb	≤ 25 ˚C; IDM = 25 A;	-	1	J
		VDD	≤ 20 V; inductive load
EDRM	Repetitive clamping energy	Tmb	≤ 85 ˚C; IDM = 16 A;	-	80	mJ
		VDD	≤ 20 V; f = 250 Hz

ESD LIMITING VALUE

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT

VC	Electrostatic discharge capacitor	Human body model;	-	2	kV
	voltage	C = 250 pF; R = 1.5 kΩ

1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.

2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.

3 The input voltage for which the overload protection circuits are functional.

4 For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.

5 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for PDSM, which is always the case when VDS is less than VDDP(P) maximum.

April 1993

Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistor				BUK102-50DL
Logic level TOPFET

THERMAL CHARACTERISTICS

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT

	Thermal resistance
Rth j-mb	Junction to mounting base	-	-	0.8	1	K/W
Rth j-a	Junction to ambient	in free air	-	60	-	K/W
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT

V(CL)DSS	Drain-source clamping voltage	VIS = 0 V; ID = 10 mA	50	-	-	V
V(CL)DSS	Drain-source clamping voltage	VIS = 0 V; IDM = 4 A; tp £ 300 ms;	-	-	70	V
		d £ 0.01				mA
IDSS	Zero input voltage drain current	VDS = 12 V; VIS = 0 V	-	0.5	10	mA
IDSS	Zero input voltage drain current	VDS = 50 V; VIS = 0 V	-	1	20	mA
IDSS	Zero input voltage drain current	VDS = 40 V; VIS = 0 V; Tj = 125 ˚C	-	10	100	mA
RDS(ON)	Drain-source on-state	VIS = 5 V; IDM = 25 A; tp £ 300 ms;	-	30	35	mW
	resistance6	d £ 0.01

OVERLOAD PROTECTION CHARACTERISTICS

TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.

SYMBOL	PARAMETER	CONDITIONS					MIN.	TYP.	MAX.	UNIT

EDS(TO)	Short circuit load protection2	Tmb = 25 ˚C; L £ 10 mH; RL = 10 mW
EDS(TO)	Overload threshold energy	VDD = 13	V; VIS = 5 V				-	1.1	-	J
td sc	Response time	VDD = 13	V; VIS = 5 V				-	0.8	-	ms
I	Drain current3	V = 13	V; V		IS	= 5 V	-	75	-	A
D(SC)		DD			IS
I	Peak drain current4	V = 5 V; V		DD	= 13 V		-	200	-	A
DM(SC)		IS		DD
	Over temperature protection	VIS = 5 V; from ID ³ 2 A5
Tj(TO)	Threshold junction temperature	VIS = 5 V; from ID ³ 2 A5					150	-	-	˚C

TRANSFER CHARACTERISTIC

Tmb = 25 ˚C

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT

gfs	Forward transconductance	VDS = 10 V; IDM = 25 A tp £ 300 ms;	17	28	-	S
		d £ 0.01

1 Continuous input voltage. The specified pulse width is for the drain current.

2 Refer to OVERLOAD PROTECTION LIMITING VALUES.

3 Continuous drain-source supply voltage. Pulsed input voltage.

4 Continuous input voltage. Momentary short circuit load connection. (The higher peak current is due to the effect of capacitance Cgd).

5 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID ensures this condition.

April 1993

Rev 1.100

Philips Semiconductors	Product specification

PowerMOS transistor	BUK102-50DL
Logic level TOPFET

INPUT CHARACTERISTICS

Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.

SYMBOL	PARAMETER	CONDITIONS		MIN.	TYP.	MAX.	UNIT

VIS(TO)	Input threshold voltage	VDS = 5 V; ID = 1 mA		1.0	1.5	2.0	V
IIS	Input supply current	normal operation;	VIS = 5 V	100	200	350	μA
	Protection reset voltage1		VIS = 4 V	-	160	270	μA
V	Protection reset voltage1		T = 25 ˚C	2.0	2.6	3.5	V
ISR			j
			Tj = 150 ˚C	1.0	-	-
IISL	Input supply current	protection latched;	VIS = 5 V	-	330	650	μA
			VIS = 3.5 V	-	240	430	μA
V(BR)IS	Input breakdown voltage	II = 10 mA		6	-	-	V
RIG	Input series resistance		Tj = 25 ˚C	-	33	-	kΩ
	to gate of power MOSFET		Tj = 150 ˚C	-	50	-	kΩ

SWITCHING CHARACTERISTICS

Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figure and test circuit.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT

td on	Turn-on delay time	VDD = 13 V; VIS = 5 V	-	30	-	μs
tr	Rise time	resistive load RL = 2.1 Ω	-	150	-	μs
td off	Turn-off delay time	VDD = 13 V; VIS = 0 V	-	120	-	μs
tf	Fall time	resistive load RL = 2.1 Ω	-	120	-	μs

REVERSE DIODE LIMITING VALUE

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT

IS	Continuous forward current	Tmb ≤ 25 ˚C; VIS = 0 V	-	45	A

REVERSE DIODE CHARACTERISTICS

Tmb = 25 ˚C

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT

VSDO	Forward voltage	IS = 45 A; VIS = 0 V; tp = 300 μs	-	1.0	1.5	V
t	Reverse recovery time	not applicable2	-	-	-	-
rr

1 The input voltage below which the overload protection circuits will be reset.

2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.

April 1993

Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistor				BUK102-50DL
Logic level TOPFET

ENVELOPE CHARACTERISTICS

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT

Ld	Internal drain inductance	Measured from contact screw on	-	3.5	-	nH
		tab to centre of die
Ld	Internal drain inductance	Measured from drain lead 6 mm	-	4.5	-	nH
		from package to centre of die
Ls	Internal source inductance	Measured from source lead 6 mm	-	7.5	-	nH
		from package to source bond pad

120	PD%				Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0	0	20	40	60	80	100	120	140
	0	20	40	60	80	100	120	140
					Tmb /	C
Fig.2. Normalised limiting power dissipation.
		PD% = 100×PD/PD(25 ˚C) = f(Tmb)

ID%				Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0	20	40	60	80	100	120	140
				Tmb /	C
Fig.3. Normalised continuous drain current.
ID% = 100×ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V

ID & IDM / A

BUK102-50DL

1000

Overload protection characteristics not shown

	VDS/ID
100	=
	RDS(ON)

		tp =
		100 us
10	DC	1 ms
10
		10 ms
		10 ms
		100 ms

1	1		10		100
	1		10		100
			VDS / V
	Fig.4.	Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
10	Zth / (K/W)				BUK102-50DL
10
1	D =
1
	0.5
	0.2
0.1	0.1
	0.05
	0.02
0.01	0		P	tp	D =	tp
0.01	0		D		D =	T
					T	t
0.001					T
0.001
1E-07		1E-05	1E-03		1E-01	1E+01
			t / s

Fig.5. Transient thermal impedance.

Zth j-mb = f(t); parameter D = tp/T

April 1993

Rev 1.100

Philips Semiconductors	Product specification

PowerMOS transistor	BUK102-50DL
Logic level TOPFET

ID / A				BUK102-50DL
80
70		VIS / V =		6
70
60				5.5
60				5
				5
50				4.5
				4.5
40				4
				4
30
20				3.5
20
10				3
10
0
0	1	2	3	4	5
		VDS / V

Fig.6. Typical on-state characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VIS; tp = 2 ms

RDS(ON) / mOhm

BUK102-50DL

80
70	VIS / V =
70
60	3.5	4	4.5	5	5.5
60		4	4.5	5	6
					6
50
40
30
20
10
0
0	20		40	60	80
			ID / A

Fig.7. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VIS; tp = 2 ms

a	Normalised RDS(ON) = f(Tj)

1.5
1.0
0.5
0
-60	-40 -20	0	20	40	60	80 100 120 140
				Tj /	C
Fig.8. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VIS = 5 V

td sc / ms		BUK102-50DL
10
		PDSM
1
0.1
0.1	1	10

PDS / kW

Fig.9. Typical overload protection characteristics.
td sc = f(PDS); conditions: VIS						³	4 V; Tj = 25 ˚C.
PDSM%
120
100
80
60
40
20
0
-60	-40	-20	0	20	40	60	80	100	120	140
					Tmb / C
Fig.10. Normalised limiting overload dissipation.
	PDSM% =100×PDSM/PDSM(25 ˚C) = f(Tmb)
Energy & Time									BUK102-50DL
1.5
				Energy / J
1.0
				Time / ms
0.5
							Tj(TO)
0
-60	-20		20	60	100		140	180		220
					Tmb / C

Fig.11. Typical overload protection characteristics. Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mW

April 1993

Rev 1.100

Philips Semiconductors	Product specification

PowerMOS transistor	BUK102-50DL
Logic level TOPFET

ID / A									BUK102-50DL
50
40
30								typ.
20
10
0
50					60				70
					VDS / V
Fig.12. Typical clamping characteristics, 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp									≤ 50 μs
VIS(TO) / V
2					max.
2
					typ.
1					min.
1
0
-60	-40	-20	0	20	40	60	80	100	120 140
					Tj /	C
	Fig.13.		Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V

IISL & IIS / uA			BUK102-50DL
600
500		PROTECTION LATCHED
400
			IISL
300	RESET
200			IIS
200
100			NORMAL
0
0	2	4	6
		VIS / V

Fig.14. Typical DC input characteristics, Tj = 25 ˚C. IISL & IIS = f(VIS); protection latched & normal operation

IS / A								BUK102-50DL
200
150
100
50
0
0	0.2	0.4	0.6	0.8	1	1.2	1.4	1.6	1.8	2
					VSD / V

Fig.15. Typical reverse diode current, Tj = 25 ˚C. IS = f(VSDS); conditions: VIS = 0 V; tp = 250 μs

	VDD
RL
TOPFET	D
TOPFET
I	D.U.T.
P	D.U.T.
R I
VIS	S
	ID measure
	0V
	0R1

Fig.16. Test circuit for resistive load switching times.

VIS / V & VDS / V				BUK102-50DL
15
	VDS
10
			VIS
5
0
0	200	400	600	800	1000

time / us

Fig.17. Typical switching waveforms, resistive load. VDD = 13 V; RL = 1.1 Ω; RI = 50 Ω, Tj = 25 ˚C.

April 1993

Rev 1.100

Philips Semiconductors	Product specification

PowerMOS transistor	BUK102-50DL
Logic level TOPFET

EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0

0	20	40	60	80		100	120	140
				Tmb / C
Fig.18. Normalised limiting clamping energy.
EDSM% = f(Tmb); conditions: ID = 25 A; VIS = 10 V
VDS		V(CL)DSS
VDS
		VDD					+	VDD
0							+
ID				L
ID
0					VDS		-
0
VIS				D
VIS				D
		TOPFET						-ID/100
								-ID/100
0		I		D.U.T.
0		I	P
			P
		Schottky				R 01
		RIS		S		shunt
Fig.19.	Clamping energy test circuit, RIS = 50 Ω.
E	DSM	= 0.5 × LI2	× V	(CL )DSS	/(V	(CL )DSS	- V	)
	DSM	D		(CL )DSS		(CL )DSS	DD

Idss
1 mA
100 uA
10 uA
					typ.
1 uA
100 nA
0	20	40	60	80	100	120	140
				Tj / C

Fig.20. Typical off-state leakage current. IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V.

Iiso & Iisl normalised to 25 C

1.5
1
0.5
-60	-20	20	60	100	140	180
			Tj / C

Fig.21. Normalised input currents (normal & latched). IISO/IISO25˚C & IISL/IISL25˚C = f(Tj); VIS = 5 V

April 1993

Rev 1.100

Philips Semiconductors Product specification

	PowerMOS transistor	BUK102-50DL
	Logic level TOPFET
	MECHANICAL DATA
	Dimensions in mm	4,5
	Net Mass: 2 g	4,5
	Net Mass: 2 g	max
	10,3
	max	1,3
	3,7	1,3
	3,7
	2,8	5,9
		min
		15,8
		max

	3,0 max	3,0
	not tinned	3,0
	not tinned

		13,5
		min
1,3
max	1 2 3
(2x)		0,9 max (3x)	0,6
			0,6
	2,54 2,54		2,4
	2,54 2,54

Fig.22. TO220AB; pin 2 connected to mounting base.

Notes

1.Accessories supplied on request: refer to mounting instructions for TO220 envelopes.

2.Epoxy meets UL94 V0 at 1/8".

April 1993

Rev 1.100

Philips Semiconductors	Product specification

PowerMOS transistor	BUK102-50DL
Logic level TOPFET

DEFINITIONS

Data sheet status

Objective specification	This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

April 1993

Rev 1.100

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