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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Decade Counter

High±Performance Silicon±Gate CMOS

The MC74HC4017 is identical in pinout to the standard CMOS MC14017B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC4017 uses a five stage Johnson counter and decoding logic to provide high±speed operation. This device also has an active±high, as well as active±low clock input.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 176 FETs or 44 Equivalent Gates

LOGIC DIAGRAM

14		3	Q0
CLOCK		2	Q1
CLOCK 13		4	Q2
ENABLE		7	Q2
ENABLE			Q3
			Q3
		10	Q4	DECADE
		1	Q5	DECADE
		1	Q5	OUTPUTS
		5	Q6
		6	Q7
		9	Q8
		11	Q9
		12	CARRY OUT
			CARRY OUT
RESET	15	PIN 16 = VCC
RESET		PIN 8 = GND
		PIN 8 = GND

MC74HC4017

		N SUFFIX
	16	PLASTIC PACKAGE
	16	CASE 648±08
		CASE 648±08
		1

	D SUFFIX
16	SOIC PACKAGE
1	CASE 751B±05
ORDERING INFORMATION
MC74HCXXXXN	Plastic
MC74HCXXXXD	SOIC

PIN ASSIGNMENT

Q5	1	16	VCC


Q1	2	15	RESET
Q0	3	14	CLOCK

Q2	4	13	CLOCK ENABLE

Q6	5	12	CARRY OUT

Q7	6	11	Q9

Q3	7	10	Q4

GND	8	9	Q8

10/95

Motorola, Inc. 1995

REV 6

MC74HC4017

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit

VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 1.5 to VCC + 1.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
	SOIC Package²		500

Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP or SOIC Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C

SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit

VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC
				VCC	± 55 to
Symbol	Parameter	Test Conditions		V	25_C	v 85_C	v 125_C	Unit

VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	1.5	1.5	1.5	V
	Voltage	\|Iout\| v 20 μA		4.5	3.15	3.15	3.15
				6.0	4.2	4.2	4.2

VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	0.3	0.3	0.3	V
	Voltage	\|Iout\| v 20 μA		4.5	0.9	0.9	0.9
				6.0	1.2	1.2	1.2

VOH	Minimum High±Level Output	Vin = VIH or VIL		2.0	1.9	1.9	1.9	V
	Voltage	\|Iout\| v 20 μA		4.5	4.4	4.4	4.4
				6.0	5.9	5.9	5.9

		Vin = VIH or VIL	\|Iout\| v 4.0 mA	4.5	3.98	3.84	3.70
			\|Iout\| v 5.2 mA	6.0	5.48	5.34	5.20
VOL	Maximum Low±Level Output	Vin = VIH or VIL		2.0	0.1	0.1	0.1	V
	Voltage	\|Iout\| v 20 μA		4.5	0.1	0.1	0.1
				6.0	0.1	0.1	0.1

		Vin = VIH or VIL	\|Iout\| v 4.0 mA	4.5	0.26	0.33	0.40
			\|Iout\| v 5.2 mA	6.0	0.26	0.33	0.40
Iin	Maximum Input Leakage Current	Vin = VCC or GND		6.0	± 0.1	± 1.0	± 1.0	μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND		6.0	8	80	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA

MC74HC4017

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC
		VCC	± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit

fmax	Maximum Clock Frequency (50% Duty Cycle)	2.0	4.0	3.2	2.6	MHz
	(Figures 1 and 9)	4.5	20	16	13
		6.0	24	19	15

tPLH,	Maximum Propagation Delay, Clock to Q	2.0	230	290	345	ns
tPHL	(Figures 1 and 9)	4.5	46	58	69
		6.0	39	49	59

tPLH,	Maximum Propagation Delay, Clock to Carry Out	2.0	230	290	345	ns
tPHL	(Figures 2 and 9)	4.5	46	58	69
		6.0	39	49	59

tPLH,	Maximum Propagation Delay, Reset to Q	2.0	230	290	345	ns
tPHL	(Figures 3 and 9)	4.5	46	58	69
		6.0	39	49	59

tPLH	Maximum Propagation Delay, Reset to Carry Out	2.0	230	290	345	ns
	(Figures 3 and 9)	4.5	46	58	69
		6.0	39	49	59

tPLH,	Maximum Propagation Delay, Clock Enable to Q	2.0	250	315	375	ns
tPHL	(Figures 4 and 9)	4.5	50	63	75
		6.0	43	54	64

tPLH,	Maximum Propagation Delay, Clock Enable to Carry Out	2.0	250	315	375	ns
tPHL	(Figures 5 and 9)	4.5	50	63	75
		6.0	43	54	64

tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 8 and 9)	4.5	15	19	22
		6.0	13	16	19

Cin	Maximum Input Capacitance	Ð	10	10	10	pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

			Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Package)*			35		pF

* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA

MC74HC4017

TIMING REQUIREMENTS (Input tr = tf = 6 ns)t

			Guaranteed Limit
		VCC
		VCC	± 55 to	v	_		v	_
Symbol	Parameter	V	_	v	_	C	v	_	Unit
Symbol	Parameter		25 C	85		C		125 C	Unit
tsu	Minimum Setup Time, Clock Enable to Clock	2.0	50	65				75	ns
	(Figure 6)	4.5	10	13				15
		6.0	9	11				13

tsu	Minimum Setup Time, Clock Enable to Clock (Inhibit Count)	2.0	50	65				75	ns
	(Figure 6)	4.5	10	13				15
		6.0	9	11				13

th	Minimum Hold Time, Clock to Clock Enable	2.0	50	65				75	ns
	(Figure 6)	4.5	10	13				15
		6.0	9	11				13

trec	Minimum Recovery Time, Reset to Clock	2.0	100	125				150	ns
	(Figure 7)	4.5	20	25				30
		6.0	17	21				26

tw	Minimum Pulse Width, Clock Input	2.0	80	100				120	ns
	(Figure 2)	4.5	16	20				24
		6.0	14	17				20

tw	Minimum Pulse Width, Reset Input	2.0	80	100				120	ns
	(Figure 3)	4.5	16	20				24
		6.0	14	17				20

tw	Minimum Pulse Width, Clock Enable Input	2.0	80	100				120	ns
	(Figure 4)	4.5	16	20				24
		6.0	14	17				20

tr, tf	Maximum Input Rise and Fall Times	2.0	1000	1000			1000		ns
	(Figure 1)	4.5	500	500				500
		6.0	400	400				400

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

FUNCTION TABLE

		Clock
Clock		Enable		Reset	Output State*

	L		X	L	no change
	X		H	L	no change
	X		X	H	reset counter, Q0 = H, Q1± Q9 = L, C0 = H
			L	L	advance to next state
			X	L	no change
	X			L	no change
	H			L	advance to next state

X = Don't care

* Carry Out = H for Q0, Q1, Q2, Q3, or Q4 = H; Carry Out = L otherwise.

PIN DESCRIPTIONS

INPUTS

Clock (Pin 14)

Counter clock input. While Clock Enable is low, a low±to± high transition on this input advances the counter to its next state.

Reset (Pin 15)

Asynchronous counter reset input. A high level at this input initializes the counter and forces Q0 and Carry Out to a high, Q1±Q9 are forced to a low level.

Clock Enable (Pin 13)

Active±low clock enable input. A low level on this input allows the device to count. A high level on this input inhibits the counting operation. This input may also be used as a

negative±edge clock input. using Clock (Pin 14) as an active±high enable pin.

OUTPUTS

Q0 ± Q9 (Pins 3, 2, 4, 7, 10, 1, 5, 6, 9, 11)

Decoded decade counter outputs. Each of these outputs is high for one clock period only.

Carry Out (Pin 12)

Cascading output pin. This output is used either as a cascading output or a symmetrical divide±by±ten output. This output goes low when a count of five is reached and high when the counter advances to zero or when reset. When the counters are cascaded this output provides a rising±edge signal for the clock input of the next counter stage.

MOTOROLA

MC74HC4017

SWITCHING WAVEFORMS

	tr	tf
	90%	VCC
	50%
CLOCK	10%	GND
	tw
	1/fmax
	tPLH	tPHL

	90%
Q	50%
	10%
	tTLH	tTHL

Figure 1.

RESET	VCC
RESET	50%
	GND
	tw
	tPHL
Q1±Q9	50%
	VCC
	tPLH
	GND
Q0, CARRY OUT	50%

Figure 3.

CLOCK	VCC
CLOCK	50%
ENABLE	GND
tPHL	tPLH
CARRY	50%
OUT

Figure 5.

		VCC
	CLOCK	50%
	CLOCK	GND
		GND
		trec
	RESET	VCC
	RESET	50%
		50%
		GND

		VCC
	CLOCK	50%
		GND
		tw
	tPLH	tPHL
	tPLH
	CARRY	50%
	OUT	50%
	OUT

Figure 2.

	tw	VCC
	50%	VCC
	50%
CLOCK		GND
ENABLE	tPLH	tPHL
Q	50%

Figure 4.

		VALID
CLOCK		VCC
CLOCK	50%
ENABLE	50%	GND
ENABLE

	t	th
	su	VCC
		VCC
CLOCK		50%
CLOCK		GND
		GND

Figure 6.

tTLH	tTHL
90%

Q0 ± Q9, 10%

CARRY OUT

	Figure 8.
		TEST POINT

		OUTPUT
DEVICE
DEVICE
UNDER			CL*
TEST

* Includes all probe and jig capacitance

Figure 7.

Figure 9. Test Circuit

MOTOROLA

MC74HC4017

TIMIING DIAGRAM

CLOCK

ENABLE

RESET

CARRY

OUT

MOTOROLA

		MC74HC4017
		EXPANDED LOGIC DIAGRAM
D	Q
		3	Q0
C	Q		Q0
C	Q
R
RESET 15		2	Q1
RESET 15			Q1
D	Q	4	Q2
			Q2
C	Q
R		7	Q3
			Q3
CLOCK 14		10	Q4
			Q4

		1	Q5
			Q5
CLOCK 13		5	Q6
			Q6

ENABLE	Q
D	Q	6
		6	Q7
			Q7
C	Q
R		9
		9	Q8
D	Q	11	Q9
C	Q	12	CARRY
R		12	CARRY
R			OUT
			OUT
D	Q
C	Q
R

MOTOROLA

MC74HC4017

TYPICAL APPLICATIONS

VCC

5	1	Q5	HC4017	16
	2		VCC	15
		Q1	RESET
	3	Q0	CLOCK	14	OSC.
2	4	Q2	CLOCK	13
	5		ENABLE	12	10
6		Q6
	6		CARRY OUT	11	(NO FEEDBACK REQUIRED)
7		Q7	Q9		9
	7			10
3		Q3	Q4		4
	8			9
		GND	Q8		8

					1/6 HC04
					OUTPUT

BUFFER

(OPTIONAL TO PREVENT SPURIOUS RESET.)

Figure 10 shows a divide by 2 through 10 circuit using one HC4017. Please note that since Reset is asynchronous, the output pulse widths are narrow.

Figure 10. 2 Through 10 Circuit

C	R			C	R			C	R
C	HC4017			C	HC4017			C	HC4017
CE	HC4017			CE	HC4017			CE	HC4017
CE				CE				CE
Q0	Q1	Q8	Q9	Q0	Q1	Q8	Q9	Q1	Q8	Q9
	9 DECODED				8 DECODED				8 DECODED
	OUTPUTS				OUTPUTS				OUTPUTS
CLOCK			HC08					HC08
CLOCK	FIRST STAGE			INTERMEDIATE STAGES					LAST STAGE
	FIRST STAGE			INTERMEDIATE STAGES					LAST STAGE

Figure 11 shows a technique for cascading the counters to extend the number of decoded output states. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).

Figure 11. Counter Expansion

MOTOROLA

MC74HC4017

				OUTLINE DIMENSIONS
					N SUFFIX
	±A				PLASTIC PACKAGE		NOTES:
	±				CASE 648±08		1. DIMENSIONING AND TOLERANCING PER ANSI
	±				CASE 648±08			Y14.5M, 1982.
16	9				ISSUE R		2.	CONTROLLING DIMENSION: INCH.
16	9				ISSUE R		3. DIMENSION L TO CENTER OF LEADS WHEN
	B						3. DIMENSION L TO CENTER OF LEADS WHEN
	B							FORMED PARALLEL.
1	8						4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1	8						5.	ROUNDED CORNERS OPTIONAL.
									INCHES		MILLIMETERS
	F	C			L			DIM	MIN	MAX	MIN	MAX
		C			L			A	0.740	0.770	18.80	19.55
	S							B	0.250	0.270	6.35	6.85
	S							C	0.145	0.175	3.69	4.44
								D	0.015	0.021	0.39	0.53
			±T	SEATING				F	0.040	0.070	1.02	1.77
			±T	SEATING				G	0.040	0.070	1.02	1.77
			±	PLANE				G		0.100 BSC		2.54 BSC
		K	±			M		H		0.050 BSC		1.27 BSC
	H							H		0.050 BSC		1.27 BSC
					J			J	0.008	0.015	0.21	0.38
					J			J	0.008	0.015	0.21	0.38
	G							K	0.110	0.130	2.80	3.30
	D 16 PL							L	0.295	0.305	7.50	7.74
	0.25 (0.010)	M	T	A M				M	0°	10°	0°	10°
	0.25 (0.010)	M	T	A M				S	0.020	0.040	0.51	1.01

	D SUFFIX
	PLASTIC SOIC PACKAGE
±A	CASE 751B±05
±	ISSUE J
16	9

		±B P 8 PL
1	8	±	0.25 (0.010) M	B M
			0.25 (0.010) M	B M

G
K		F
K		°
		R X 45
	C
±T		J
SEATING±	M	J
SEATING±	M

PLANE	D 16 PL

0.25 (0.010) M T B S A S

NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

	MILLIMETERS		INCHES
DIM	MIN	MAX	MIN	MAX
A	9.80	10.00	0.386	0.393
B	3.80	4.00	0.150	0.157
C	1.35	1.75	0.054	0.068
D	0.35	0.49	0.014	0.019
F	0.40	1.25	0.016	0.049
G	1.27 BSC		0.050 BSC
J	0.19	0.25	0.008	0.009
K	0.10	0.25	0.004	0.009
M	0°	7°	0°	7°
P	5.80	6.20	0.229	0.244
R	0.25	0.50	0.010	0.019

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ªTypicalº parameters can and do vary in different applications. All operating parameters, including ªTypicalsº must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:
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◊ CODELINE MC74HC4017/D

*MC74HC4017/D*

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