SPI Packets

Host-to-Decoder Packet Descriptions

may be useful in acquiring transmitted time information. The value after reset = 0.

DECREMENT TEMPORARY ADDRESS (DTA) ENABLE COUNTER

When a bit in this word is set, the corresponding temporary address enable counter is decremented by 1. When a bit is cleared, the corresponding temporary address enable counter is not affected. When a temporary address enable counter reaches 0, the temporary address is disabled.The value after reset = 0.

Receiver Line Control Packet

This packet gives the host control over the settings on the receiver control lines (S0-S7) in all modes except reset. In reset, the receiver control lines are in high impedance settings. The ID for the Receiver Line Control Packet is 15 (decimal).

Table B-10 Receiver Line Control Packet Bit Assignments

FORCE RECEIVER SETTING (FRS)

Setting a bit to one will cause the corresponding CLS bit in this packet to override the internal receiver control settings on the corresponding receiver control line (S0–S7). Clearing a bit gives control of the corresponding receiver control lines (S0–S7) back to the FLEXchip IC. The value after reset = 0.

CONTROL LINE SETTING (CLS)

If the corresponding FRS bit was set in this packet, these bits define what setting should be applied to the corresponding receiver control lines. The value after reset = 0.