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- •Advance Information
- •Figure 1 MC68175 Functional Block Diagram
- •Table of Contents
- •Features
- •Additional Support
- •Documentation
- •Features
- •Signal/Connection Descriptions
- •Signal Groupings
- •Power Input and Monitoring
- •Processor Clock
- •Test and Reset
- •Input
- •Output
- •Input
- •Input
- •Input
- •Current Symbol Inputs
- •Input
- •Input
- •Serial Peripheral Interface (SPI)
- •Receiver Control Port
- •Specifications
- •Introduction
- •Maximum Ratings
- •TSTG
- •Thermal characteristics
- •Not available
- •DC Electrical Characteristics
- •ITSI
- •AC Electrical Characteristics
- •Initialization Timing
- •tSTART
- •tRESET
- •tRHRL
- •tOWRL
- •RESET Timing
- •tRLRH
- •tRHRL
- •Serial Peripheral Interface (SPI) Timing
- •tCYC
- •tLEAD1
- •tLAG1
- •tRDY
- •tRDY
- •tLEAD2
- •tLAG2
- •tDIS
- •tSSH
- •tSCKH
- •tSCKL
- •Packaging
- •Pin-out and Package Information
- •TQFP Package Description
- •TOUT0
- •TOUT3
- •TOUT2
- •TOUT1
- •TOUTEN
- •LOBAT
- •READY
- •EXTS1
- •TEST
- •EXTS0
- •XTAL
- •EXTAL
- •SYMCLK
- •MOSI
- •MISO
- •TOUTSEL
- •RESET
- •CLKOUT
- •CLKOUT
- •RESET
- •TOUT3
- •EXTAL
- •TOUTEN
- •EXTS0
- •TOUTSEL
- •EXTS1
- •SYMCLK
- •LOBAT
- •TEST
- •MISO
- •TOUT0
- •MOSI
- •TOUT1
- •READY
- •TOUT2
- •XTAL
- •Ordering Drawings
- •Design Considerations
- •Thermal Design Considerations
- •Application Design Considerations
- •Ordering Information
- •FLEX Overview
- •FLEX Signal Structure
- •FLEX Message Word Definitions
- •Numeric Data Message
- •Message Fill Rules
- •Special Format Numeric
- •Hex/Binary Message
- •Message Content
- •Fragment Termination
- •Message Header
- •Alphanumeric Message
- •Message Content
- •Message Termination
- •Enhanced Fragmentation Rules
- •Secure Message
- •Message Content
- •Message Termination
- •FLEX Encoding and Decoding Rules
- •FLEX Encoding Rules
- •FLEX Decoding Rules
- •FLEX Character Sets and Rules
- •Alphanumeric Character Set
- •Numeric Character Set
- •Spare
- •Space
- •Space
- •FLEX Local Time And Date
- •Month/Day/Year
- •Second/Minute/Hour
- •Accurate Seconds/Daylight Savings Time/Time Zone
- •RESERVED
- •FLEX CAPCODES
- •Idle Word (Illegal Address)
- •Long Address 1
- •Short Address
- •Long Address 3
- •Long Address 4
- •Short Address (Reserved)
- •Info Service Address
- •Network Address
- •Temporary Address
- •Operator Messaging Address
- •Short Address (Reserved)
- •Long Address 2
- •1F7FFF–1FFFFE
- •Idle Word (Illegal Address)
- •1FFFFF
- •Long Address 1
- •Long Address 2
- •Long Address 1
- •Long Address 3
- •Long Address 1
- •Long Address 4
- •Long Address 2
- •Long Address 3
- •Long Address 2
- •Long Address 4
- •CAPCODE Type
- •fffbU1234567
- •fffbU123456789
- •RfffbU1234567890
- •Standard Frame and Phase Embedding Rules
- •CAPCODE Alpha Character Definition
- •CAPCODE to Binary Conversion
- •Short CAPCODE
- •Long CAPCODE 2,101,249 to 1,075,843,072
- •Long CAPCODE 1,075,843,073 to 3,223,326,720
- •Long CAPCODE 3,223,326,721 to 4,297,068,542
- •Binary to CAPCODE Conversion
- •CAPCODE Assignments
- •SPI Packets
- •Packet Communication Initiated by the Host
- •Packet Communication Initiated by the FLEXchip IC
- •1. The FLEXchip IC drives the READY pin low.
- •Host-to-Decoder Packet Map
- •Decoder-to-Host Packet Map
- •Host-to-Decoder Packet Descriptions
- •Checksum Packet
- •Configuration Packet
- •Oscillator Frequency Difference (OFD)
- •Signal Polarity (SP)
- •Normal
- •Normal
- •Normal
- •Inverted
- •Inverted
- •Normal
- •Inverted
- •Inverted
- •Synchronous Mode Enable (SME)
- •Maximum Off Time (MOT)
- •Clock Output Disable (COD)
- •Minute Timer Enable (MTE)
- •Low Battery Polarity (LBP)
- •Control Packet
- •Force Frame (FF) 0–7
- •Single Phase Mode (SPM)
- •Phase Select (PS)
- •Send Block Information (SBI) words 2-4
- •Minute Timer Clear (MTC)
- •Turn On Decoder (ON)
- •All Frame Mode Packet
- •Decrement All Frame (DAF) Counter
- •Force All Frame (FAF) Mode
- •Decrement Temporary Address (DTA) Enable Counter
- •Receiver Line Control Packet
- •Force Receiver Setting (FRS)
- •Control Line Setting (CLS)
- •Receiver Control Configuration Packets
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Receiver Warm Up Setting Packets
- •Setting Number (s)
- •Warm Up 1
- •Warm Up 2
- •Warm Up 3
- •Warm Up 4
- •Warm Up 5
- •Step Enable (SE)
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •3200 sps Sync Setting Packets
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Receiver On Setting Packets
- •Setting Number (s)
- •1600 sps Sync
- •3200 sps Data
- •1600 sps Data
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Receiver Shut Down Setting Packets
- •Setting Number (s)
- •Shut Down 1
- •Shut Down 2
- •Step Enable (SE)
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Frame Assignment Packets
- •Frame range (f)
- •Frame 127
- •Frame 112
- •Frame 111
- •Frame 96
- •Frame 95
- •Frame 80
- •Frame 79
- •Frame 64
- •Frame 63
- •Frame 48
- •Frame 47
- •Frame 32
- •Frame 31
- •Frame 16
- •Frame 15
- •Frame 0
- •Assigned Frame (AF)
- •User Address Enable Packet
- •User Address Assignment Packets
- •User Address Word Number (a0–a3)
- •Long Address (LA)
- •Tone-Only Address (TOA)
- •Address word (A0–A20)
- •Decoder-to-Host Packet Descriptions
- •Block Information Word Packet
- •Address Packet
- •Priority Address (PA)
- •Phase (p)
- •Long Address type (LA)
- •Address Index (AI)
- •Tone Only Address (TOA)
- •Word number (WN) of vector (2–87)
- •Unused bits (x)
- •Vector Packet
- •Short Message / Tone Only Vector
- •Numeric Vector Packet
- •Vector Type Identifier (V)
- •Additional Bit Descriptors
- •Vector Type Identifier (V)
- •Secure
- •Alphanumeric
- •Hex / Binary
- •Additional Bit Descriptors
- •Short Instruction Vector
- •Message Packet
- •Status Packet
- •Frame Info Valid (FIV)
- •Current frame number (f)
- •Synchronous Mode (SM)
- •Low Battery (LB)
- •Current System Cycle Number (c)
- •Synchronous Mode Update (SMU)
- •Low Battery Update (LBU)
- •Minute Time-out (MT)
- •End Of Frame (EOF)
- •Buffer Overflow Error (BOE)
- •Unused bits (x)
- •Part ID Packet
- •Model (MDL)
- •Compatibility ID (CID)
- •Revision (REV)
- •Application Notes
- •Receiver Control
- •Introduction
- •1. what setting is applied to the control lines,
- •2. how long to apply the setting, and
- •Receiver Settings at Reset
- •Normal Receiver Warm Up Sequence
- •First Receiver Warm Up Sequence
- •Receiver Shut Down Sequence
- •Miscellaneous Receiver States
- •Low Battery Detection
- •Message Building
- •ADDRESS 1
- •ADDRESS 2
- •LONG ADDRESS 3 WORD 1
- •LONG ADDRESS 3 WORD 2
- •VECTOR 1
- •VECTOR 2
- •MESSAGE 1, 1
- •MESSAGE 1, 2
- •VECTOR 3
- •MESSAGE 1, 3
- •MESSAGE 3, 1
- •MESSAGE 2, 1
- •MESSAGE 2, 2
- •MESSAGE 2, 3
- •MESSAGE 3, 2
- •MESSAGE 2, 4
- •MESSAGE 3, 3
- •ADDRESS
- •ADDRESS
- •VECTOR
- •VECTOR
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •VECTOR
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •Building a Fragmented Message
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •STATUS
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •STATUS
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •Operation of a Temporary Address
- •Group Messaging
- •FLEX Overview
- •FLEX Signal Structure
- •FLEX Message Word Definitions
- •Numeric Data Message
- •Message Fill Rules
- •Special Format Numeric
- •Hex/Binary Message
- •Message Content
- •Fragment Termination
- •Message Header
- •Alphanumeric Message
- •Message Content
- •Message Termination
- •Enhanced Fragmentation Rules
- •Secure Message
- •Message Content
- •Message Termination
- •FLEX Encoding and Decoding Rules
- •FLEX Encoding Rules
- •FLEX Decoding Rules
- •FLEX Character Sets and Rules
- •Alphanumeric Character Set
- •Numeric Character Set
- •Spare
- •Space
- •Space
- •FLEX Local Time And Date
- •Month/Day/Year
- •Second/Minute/Hour
- •Accurate Seconds/Daylight Savings Time/Time Zone
- •RESERVED
- •FLEX CAPCODES
- •Idle Word (Illegal Address)
- •Long Address 1
- •Short Address
- •Long Address 3
- •Long Address 4
- •Short Address (Reserved)
- •Info Service Address
- •Network Address
- •Temporary Address
- •Operator Messaging Address
- •Short Address (Reserved)
- •Long Address 2
- •1F7FFF–1FFFFE
- •Idle Word (Illegal Address)
- •1FFFFF
- •Long Address 1
- •Long Address 2
- •Long Address 1
- •Long Address 3
- •Long Address 1
- •Long Address 4
- •Long Address 2
- •Long Address 3
- •Long Address 2
- •Long Address 4
- •CAPCODE Type
- •fffbU1234567
- •fffbU123456789
- •RfffbU1234567890
- •Standard Frame and Phase Embedding Rules
- •CAPCODE Alpha Character Definition
- •CAPCODE to Binary Conversion
- •Short CAPCODE
- •Long CAPCODE 2,101,249 to 1,075,843,072
- •Long CAPCODE 1,075,843,073 to 3,223,326,720
- •Long CAPCODE 3,223,326,721 to 4,297,068,542
- •Binary to CAPCODE Conversion
- •CAPCODE Assignments
- •SPI Packets
- •Packet Communication Initiated by the Host
- •Packet Communication Initiated by the FLEXchip IC
- •1. The FLEXchip IC drives the READY pin low.
- •Host-to-Decoder Packet Map
- •Decoder-to-Host Packet Map
- •Host-to-Decoder Packet Descriptions
- •Checksum Packet
- •Configuration Packet
- •Oscillator Frequency Difference (OFD)
- •Signal Polarity (SP)
- •Normal
- •Normal
- •Normal
- •Inverted
- •Inverted
- •Normal
- •Inverted
- •Inverted
- •Synchronous Mode Enable (SME)
- •Maximum Off Time (MOT)
- •Clock Output Disable (COD)
- •Minute Timer Enable (MTE)
- •Low Battery Polarity (LBP)
- •Control Packet
- •Force Frame (FF) 0–7
- •Single Phase Mode (SPM)
- •Phase Select (PS)
- •Send Block Information (SBI) words 2-4
- •Minute Timer Clear (MTC)
- •Turn On Decoder (ON)
- •All Frame Mode Packet
- •Decrement All Frame (DAF) Counter
- •Force All Frame (FAF) Mode
- •Decrement Temporary Address (DTA) Enable Counter
- •Receiver Line Control Packet
- •Force Receiver Setting (FRS)
- •Control Line Setting (CLS)
- •Receiver Control Configuration Packets
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Receiver Warm Up Setting Packets
- •Setting Number (s)
- •Warm Up 1
- •Warm Up 2
- •Warm Up 3
- •Warm Up 4
- •Warm Up 5
- •Step Enable (SE)
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •3200 sps Sync Setting Packets
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Receiver On Setting Packets
- •Setting Number (s)
- •1600 sps Sync
- •3200 sps Data
- •1600 sps Data
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Receiver Shut Down Setting Packets
- •Setting Number (s)
- •Shut Down 1
- •Shut Down 2
- •Step Enable (SE)
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Frame Assignment Packets
- •Frame range (f)
- •Frame 127
- •Frame 112
- •Frame 111
- •Frame 96
- •Frame 95
- •Frame 80
- •Frame 79
- •Frame 64
- •Frame 63
- •Frame 48
- •Frame 47
- •Frame 32
- •Frame 31
- •Frame 16
- •Frame 15
- •Frame 0
- •Assigned Frame (AF)
- •User Address Enable Packet
- •User Address Assignment Packets
- •User Address Word Number (a0–a3)
- •Long Address (LA)
- •Tone-Only Address (TOA)
- •Address word (A0–A20)
- •Decoder-to-Host Packet Descriptions
- •Block Information Word Packet
- •Address Packet
- •Priority Address (PA)
- •Phase (p)
- •Long Address type (LA)
- •Address Index (AI)
- •Tone Only Address (TOA)
- •Word number (WN) of vector (2–87)
- •Unused bits (x)
- •Vector Packet
- •Short Message / Tone Only Vector
- •Numeric Vector Packet
- •Vector Type Identifier (V)
- •Additional Bit Descriptors
- •Vector Type Identifier (V)
- •Secure
- •Alphanumeric
- •Hex / Binary
- •Additional Bit Descriptors
- •Short Instruction Vector
- •Message Packet
- •Status Packet
- •Frame Info Valid (FIV)
- •Current frame number (f)
- •Synchronous Mode (SM)
- •Low Battery (LB)
- •Current System Cycle Number (c)
- •Synchronous Mode Update (SMU)
- •Low Battery Update (LBU)
- •Minute Time-out (MT)
- •End Of Frame (EOF)
- •Buffer Overflow Error (BOE)
- •Unused bits (x)
- •Part ID Packet
- •Model (MDL)
- •Compatibility ID (CID)
- •Revision (REV)
- •Application Notes
- •Receiver Control
- •Introduction
- •1. what setting is applied to the control lines,
- •2. how long to apply the setting, and
- •Receiver Settings at Reset
- •Normal Receiver Warm Up Sequence
- •First Receiver Warm Up Sequence
- •Receiver Shut Down Sequence
- •Miscellaneous Receiver States
- •Low Battery Detection
- •Message Building
- •ADDRESS 1
- •ADDRESS 2
- •LONG ADDRESS 3 WORD 1
- •LONG ADDRESS 3 WORD 2
- •VECTOR 1
- •VECTOR 2
- •MESSAGE 1, 1
- •MESSAGE 1, 2
- •VECTOR 3
- •MESSAGE 1, 3
- •MESSAGE 3, 1
- •MESSAGE 2, 1
- •MESSAGE 2, 2
- •MESSAGE 2, 3
- •MESSAGE 3, 2
- •MESSAGE 2, 4
- •MESSAGE 3, 3
- •ADDRESS
- •ADDRESS
- •VECTOR
- •VECTOR
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •VECTOR
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •Building a Fragmented Message
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •STATUS
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •STATUS
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •Operation of a Temporary Address
- •Group Messaging
SPI Packets
Host-to-Decoder Packet Descriptions
Table B-5 OFD Bits Description
OFD1 |
OFD0 |
Frequency |
|
Difference |
|||
|
|
||
|
|
|
|
|
|
|
|
0 |
0 |
±300 ppm |
|
|
|
|
|
0 |
1 |
±150 ppm |
|
|
|
|
|
1 |
0 |
±75 ppm |
|
|
|
|
|
1 |
1 |
±0 ppm |
|
|
|
|
SIGNAL POLARITY (SP)
These bits set the polarity of EXTS1 and EXTS0 input signals. The value after reset = 0. The polarity of the EXTS0 and EXTS1 bits will be determined by the receiver design.
Table B-6 SP Bit Definition
SP1 |
SP0 |
Signal Polarity |
||
EXTS1 EXTS0 |
||||
|
|
|||
|
|
|
|
|
|
|
|
|
|
0 |
0 |
Normal |
Normal |
|
|
|
|
|
|
0 |
1 |
Normal |
Inverted |
|
|
|
|
|
|
1 |
0 |
Inverted |
Normal |
|
|
|
|
|
|
1 |
1 |
Inverted |
Inverted |
|
|
|
|
|
|
FSK Modulation |
EXTS1 |
EXTS0 |
|
@ SP = 0,0 |
|||
|
|
||
|
|
|
|
|
|
|
|
+ 4800 Hz |
1 |
0 |
|
|
|
|
|
+1600 Hz |
1 |
1 |
|
|
|
|
|
- 1600 Hz |
0 |
1 |
|
|
|
|
|
- 4800 Hz |
0 |
0 |
|
|
|
|
SYNCHRONOUS MODE ENABLE (SME)
When this bit is set, a Status Packet will be automatically sent whenever the SMU (Synchronous Mode Update) bit in the Status Packet is set. The host can use the SM (Synchronous Mode) bit in the Status Packet as an in-range/out-of-range indication. The value after reset = 0.
MAXIMUM OFF TIME (MOT)
When this bit is clear, the FLEXchip IC assumes that there can be at most 4 minutes between transmitted frames on the paging system. When this bit is set, the FLEXchip IC assumes that there can be at most 1 minute between transmitted frames on the paging system. This setting is determined by the service provider. The value after reset = 0.
CLOCK OUTPUT DISABLE (COD)
When this bit is clear, a 38.4 kHz signal will be output on the CLKOUT pin. When this bit is set, the CLKOUT pin will be driven low. Note that setting and clearing this bit can cause pulses on the CLKOUT pin that are less than one half the 38.4
MOTOROLA |
MC68175/D, Preliminary |
B-9 |
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