Добавил:
student_tipo
Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз:
Предмет:
Файл:motorola / 68175DS0.PDF
Источник:
X
- •Advance Information
- •Figure 1 MC68175 Functional Block Diagram
- •Table of Contents
- •Features
- •Additional Support
- •Documentation
- •Features
- •Signal/Connection Descriptions
- •Signal Groupings
- •Power Input and Monitoring
- •Processor Clock
- •Test and Reset
- •Input
- •Output
- •Input
- •Input
- •Input
- •Current Symbol Inputs
- •Input
- •Input
- •Serial Peripheral Interface (SPI)
- •Receiver Control Port
- •Specifications
- •Introduction
- •Maximum Ratings
- •TSTG
- •Thermal characteristics
- •Not available
- •DC Electrical Characteristics
- •ITSI
- •AC Electrical Characteristics
- •Initialization Timing
- •tSTART
- •tRESET
- •tRHRL
- •tOWRL
- •RESET Timing
- •tRLRH
- •tRHRL
- •Serial Peripheral Interface (SPI) Timing
- •tCYC
- •tLEAD1
- •tLAG1
- •tRDY
- •tRDY
- •tLEAD2
- •tLAG2
- •tDIS
- •tSSH
- •tSCKH
- •tSCKL
- •Packaging
- •Pin-out and Package Information
- •TQFP Package Description
- •TOUT0
- •TOUT3
- •TOUT2
- •TOUT1
- •TOUTEN
- •LOBAT
- •READY
- •EXTS1
- •TEST
- •EXTS0
- •XTAL
- •EXTAL
- •SYMCLK
- •MOSI
- •MISO
- •TOUTSEL
- •RESET
- •CLKOUT
- •CLKOUT
- •RESET
- •TOUT3
- •EXTAL
- •TOUTEN
- •EXTS0
- •TOUTSEL
- •EXTS1
- •SYMCLK
- •LOBAT
- •TEST
- •MISO
- •TOUT0
- •MOSI
- •TOUT1
- •READY
- •TOUT2
- •XTAL
- •Ordering Drawings
- •Design Considerations
- •Thermal Design Considerations
- •Application Design Considerations
- •Ordering Information
- •FLEX Overview
- •FLEX Signal Structure
- •FLEX Message Word Definitions
- •Numeric Data Message
- •Message Fill Rules
- •Special Format Numeric
- •Hex/Binary Message
- •Message Content
- •Fragment Termination
- •Message Header
- •Alphanumeric Message
- •Message Content
- •Message Termination
- •Enhanced Fragmentation Rules
- •Secure Message
- •Message Content
- •Message Termination
- •FLEX Encoding and Decoding Rules
- •FLEX Encoding Rules
- •FLEX Decoding Rules
- •FLEX Character Sets and Rules
- •Alphanumeric Character Set
- •Numeric Character Set
- •Spare
- •Space
- •Space
- •FLEX Local Time And Date
- •Month/Day/Year
- •Second/Minute/Hour
- •Accurate Seconds/Daylight Savings Time/Time Zone
- •RESERVED
- •FLEX CAPCODES
- •Idle Word (Illegal Address)
- •Long Address 1
- •Short Address
- •Long Address 3
- •Long Address 4
- •Short Address (Reserved)
- •Info Service Address
- •Network Address
- •Temporary Address
- •Operator Messaging Address
- •Short Address (Reserved)
- •Long Address 2
- •1F7FFF–1FFFFE
- •Idle Word (Illegal Address)
- •1FFFFF
- •Long Address 1
- •Long Address 2
- •Long Address 1
- •Long Address 3
- •Long Address 1
- •Long Address 4
- •Long Address 2
- •Long Address 3
- •Long Address 2
- •Long Address 4
- •CAPCODE Type
- •fffbU1234567
- •fffbU123456789
- •RfffbU1234567890
- •Standard Frame and Phase Embedding Rules
- •CAPCODE Alpha Character Definition
- •CAPCODE to Binary Conversion
- •Short CAPCODE
- •Long CAPCODE 2,101,249 to 1,075,843,072
- •Long CAPCODE 1,075,843,073 to 3,223,326,720
- •Long CAPCODE 3,223,326,721 to 4,297,068,542
- •Binary to CAPCODE Conversion
- •CAPCODE Assignments
- •SPI Packets
- •Packet Communication Initiated by the Host
- •Packet Communication Initiated by the FLEXchip IC
- •1. The FLEXchip IC drives the READY pin low.
- •Host-to-Decoder Packet Map
- •Decoder-to-Host Packet Map
- •Host-to-Decoder Packet Descriptions
- •Checksum Packet
- •Configuration Packet
- •Oscillator Frequency Difference (OFD)
- •Signal Polarity (SP)
- •Normal
- •Normal
- •Normal
- •Inverted
- •Inverted
- •Normal
- •Inverted
- •Inverted
- •Synchronous Mode Enable (SME)
- •Maximum Off Time (MOT)
- •Clock Output Disable (COD)
- •Minute Timer Enable (MTE)
- •Low Battery Polarity (LBP)
- •Control Packet
- •Force Frame (FF) 0–7
- •Single Phase Mode (SPM)
- •Phase Select (PS)
- •Send Block Information (SBI) words 2-4
- •Minute Timer Clear (MTC)
- •Turn On Decoder (ON)
- •All Frame Mode Packet
- •Decrement All Frame (DAF) Counter
- •Force All Frame (FAF) Mode
- •Decrement Temporary Address (DTA) Enable Counter
- •Receiver Line Control Packet
- •Force Receiver Setting (FRS)
- •Control Line Setting (CLS)
- •Receiver Control Configuration Packets
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Receiver Warm Up Setting Packets
- •Setting Number (s)
- •Warm Up 1
- •Warm Up 2
- •Warm Up 3
- •Warm Up 4
- •Warm Up 5
- •Step Enable (SE)
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •3200 sps Sync Setting Packets
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Receiver On Setting Packets
- •Setting Number (s)
- •1600 sps Sync
- •3200 sps Data
- •1600 sps Data
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Receiver Shut Down Setting Packets
- •Setting Number (s)
- •Shut Down 1
- •Shut Down 2
- •Step Enable (SE)
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Frame Assignment Packets
- •Frame range (f)
- •Frame 127
- •Frame 112
- •Frame 111
- •Frame 96
- •Frame 95
- •Frame 80
- •Frame 79
- •Frame 64
- •Frame 63
- •Frame 48
- •Frame 47
- •Frame 32
- •Frame 31
- •Frame 16
- •Frame 15
- •Frame 0
- •Assigned Frame (AF)
- •User Address Enable Packet
- •User Address Assignment Packets
- •User Address Word Number (a0–a3)
- •Long Address (LA)
- •Tone-Only Address (TOA)
- •Address word (A0–A20)
- •Decoder-to-Host Packet Descriptions
- •Block Information Word Packet
- •Address Packet
- •Priority Address (PA)
- •Phase (p)
- •Long Address type (LA)
- •Address Index (AI)
- •Tone Only Address (TOA)
- •Word number (WN) of vector (2–87)
- •Unused bits (x)
- •Vector Packet
- •Short Message / Tone Only Vector
- •Numeric Vector Packet
- •Vector Type Identifier (V)
- •Additional Bit Descriptors
- •Vector Type Identifier (V)
- •Secure
- •Alphanumeric
- •Hex / Binary
- •Additional Bit Descriptors
- •Short Instruction Vector
- •Message Packet
- •Status Packet
- •Frame Info Valid (FIV)
- •Current frame number (f)
- •Synchronous Mode (SM)
- •Low Battery (LB)
- •Current System Cycle Number (c)
- •Synchronous Mode Update (SMU)
- •Low Battery Update (LBU)
- •Minute Time-out (MT)
- •End Of Frame (EOF)
- •Buffer Overflow Error (BOE)
- •Unused bits (x)
- •Part ID Packet
- •Model (MDL)
- •Compatibility ID (CID)
- •Revision (REV)
- •Application Notes
- •Receiver Control
- •Introduction
- •1. what setting is applied to the control lines,
- •2. how long to apply the setting, and
- •Receiver Settings at Reset
- •Normal Receiver Warm Up Sequence
- •First Receiver Warm Up Sequence
- •Receiver Shut Down Sequence
- •Miscellaneous Receiver States
- •Low Battery Detection
- •Message Building
- •ADDRESS 1
- •ADDRESS 2
- •LONG ADDRESS 3 WORD 1
- •LONG ADDRESS 3 WORD 2
- •VECTOR 1
- •VECTOR 2
- •MESSAGE 1, 1
- •MESSAGE 1, 2
- •VECTOR 3
- •MESSAGE 1, 3
- •MESSAGE 3, 1
- •MESSAGE 2, 1
- •MESSAGE 2, 2
- •MESSAGE 2, 3
- •MESSAGE 3, 2
- •MESSAGE 2, 4
- •MESSAGE 3, 3
- •ADDRESS
- •ADDRESS
- •VECTOR
- •VECTOR
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •VECTOR
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •Building a Fragmented Message
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •STATUS
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •STATUS
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •Operation of a Temporary Address
- •Group Messaging
- •FLEX Overview
- •FLEX Signal Structure
- •FLEX Message Word Definitions
- •Numeric Data Message
- •Message Fill Rules
- •Special Format Numeric
- •Hex/Binary Message
- •Message Content
- •Fragment Termination
- •Message Header
- •Alphanumeric Message
- •Message Content
- •Message Termination
- •Enhanced Fragmentation Rules
- •Secure Message
- •Message Content
- •Message Termination
- •FLEX Encoding and Decoding Rules
- •FLEX Encoding Rules
- •FLEX Decoding Rules
- •FLEX Character Sets and Rules
- •Alphanumeric Character Set
- •Numeric Character Set
- •Spare
- •Space
- •Space
- •FLEX Local Time And Date
- •Month/Day/Year
- •Second/Minute/Hour
- •Accurate Seconds/Daylight Savings Time/Time Zone
- •RESERVED
- •FLEX CAPCODES
- •Idle Word (Illegal Address)
- •Long Address 1
- •Short Address
- •Long Address 3
- •Long Address 4
- •Short Address (Reserved)
- •Info Service Address
- •Network Address
- •Temporary Address
- •Operator Messaging Address
- •Short Address (Reserved)
- •Long Address 2
- •1F7FFF–1FFFFE
- •Idle Word (Illegal Address)
- •1FFFFF
- •Long Address 1
- •Long Address 2
- •Long Address 1
- •Long Address 3
- •Long Address 1
- •Long Address 4
- •Long Address 2
- •Long Address 3
- •Long Address 2
- •Long Address 4
- •CAPCODE Type
- •fffbU1234567
- •fffbU123456789
- •RfffbU1234567890
- •Standard Frame and Phase Embedding Rules
- •CAPCODE Alpha Character Definition
- •CAPCODE to Binary Conversion
- •Short CAPCODE
- •Long CAPCODE 2,101,249 to 1,075,843,072
- •Long CAPCODE 1,075,843,073 to 3,223,326,720
- •Long CAPCODE 3,223,326,721 to 4,297,068,542
- •Binary to CAPCODE Conversion
- •CAPCODE Assignments
- •SPI Packets
- •Packet Communication Initiated by the Host
- •Packet Communication Initiated by the FLEXchip IC
- •1. The FLEXchip IC drives the READY pin low.
- •Host-to-Decoder Packet Map
- •Decoder-to-Host Packet Map
- •Host-to-Decoder Packet Descriptions
- •Checksum Packet
- •Configuration Packet
- •Oscillator Frequency Difference (OFD)
- •Signal Polarity (SP)
- •Normal
- •Normal
- •Normal
- •Inverted
- •Inverted
- •Normal
- •Inverted
- •Inverted
- •Synchronous Mode Enable (SME)
- •Maximum Off Time (MOT)
- •Clock Output Disable (COD)
- •Minute Timer Enable (MTE)
- •Low Battery Polarity (LBP)
- •Control Packet
- •Force Frame (FF) 0–7
- •Single Phase Mode (SPM)
- •Phase Select (PS)
- •Send Block Information (SBI) words 2-4
- •Minute Timer Clear (MTC)
- •Turn On Decoder (ON)
- •All Frame Mode Packet
- •Decrement All Frame (DAF) Counter
- •Force All Frame (FAF) Mode
- •Decrement Temporary Address (DTA) Enable Counter
- •Receiver Line Control Packet
- •Force Receiver Setting (FRS)
- •Control Line Setting (CLS)
- •Receiver Control Configuration Packets
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Receiver Warm Up Setting Packets
- •Setting Number (s)
- •Warm Up 1
- •Warm Up 2
- •Warm Up 3
- •Warm Up 4
- •Warm Up 5
- •Step Enable (SE)
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •3200 sps Sync Setting Packets
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Receiver On Setting Packets
- •Setting Number (s)
- •1600 sps Sync
- •3200 sps Data
- •1600 sps Data
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Receiver Shut Down Setting Packets
- •Setting Number (s)
- •Shut Down 1
- •Shut Down 2
- •Step Enable (SE)
- •Low Battery Check (LBC)
- •Control Line Setting (CLS)
- •Step Time (ST)
- •Frame Assignment Packets
- •Frame range (f)
- •Frame 127
- •Frame 112
- •Frame 111
- •Frame 96
- •Frame 95
- •Frame 80
- •Frame 79
- •Frame 64
- •Frame 63
- •Frame 48
- •Frame 47
- •Frame 32
- •Frame 31
- •Frame 16
- •Frame 15
- •Frame 0
- •Assigned Frame (AF)
- •User Address Enable Packet
- •User Address Assignment Packets
- •User Address Word Number (a0–a3)
- •Long Address (LA)
- •Tone-Only Address (TOA)
- •Address word (A0–A20)
- •Decoder-to-Host Packet Descriptions
- •Block Information Word Packet
- •Address Packet
- •Priority Address (PA)
- •Phase (p)
- •Long Address type (LA)
- •Address Index (AI)
- •Tone Only Address (TOA)
- •Word number (WN) of vector (2–87)
- •Unused bits (x)
- •Vector Packet
- •Short Message / Tone Only Vector
- •Numeric Vector Packet
- •Vector Type Identifier (V)
- •Additional Bit Descriptors
- •Vector Type Identifier (V)
- •Secure
- •Alphanumeric
- •Hex / Binary
- •Additional Bit Descriptors
- •Short Instruction Vector
- •Message Packet
- •Status Packet
- •Frame Info Valid (FIV)
- •Current frame number (f)
- •Synchronous Mode (SM)
- •Low Battery (LB)
- •Current System Cycle Number (c)
- •Synchronous Mode Update (SMU)
- •Low Battery Update (LBU)
- •Minute Time-out (MT)
- •End Of Frame (EOF)
- •Buffer Overflow Error (BOE)
- •Unused bits (x)
- •Part ID Packet
- •Model (MDL)
- •Compatibility ID (CID)
- •Revision (REV)
- •Application Notes
- •Receiver Control
- •Introduction
- •1. what setting is applied to the control lines,
- •2. how long to apply the setting, and
- •Receiver Settings at Reset
- •Normal Receiver Warm Up Sequence
- •First Receiver Warm Up Sequence
- •Receiver Shut Down Sequence
- •Miscellaneous Receiver States
- •Low Battery Detection
- •Message Building
- •ADDRESS 1
- •ADDRESS 2
- •LONG ADDRESS 3 WORD 1
- •LONG ADDRESS 3 WORD 2
- •VECTOR 1
- •VECTOR 2
- •MESSAGE 1, 1
- •MESSAGE 1, 2
- •VECTOR 3
- •MESSAGE 1, 3
- •MESSAGE 3, 1
- •MESSAGE 2, 1
- •MESSAGE 2, 2
- •MESSAGE 2, 3
- •MESSAGE 3, 2
- •MESSAGE 2, 4
- •MESSAGE 3, 3
- •ADDRESS
- •ADDRESS
- •VECTOR
- •VECTOR
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •VECTOR
- •MESSAGE
- •MESSAGE
- •MESSAGE
- •Building a Fragmented Message
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •STATUS
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •STATUS
- •ADDRESS 1
- •VECTOR 1
- •MESSAGE
- •Operation of a Temporary Address
- •Group Messaging
MC68175
Features
FEATURES
•FLEX paging protocol signal processor
•Sixteen programmable user address words
•Sixteen fixed temporary addresses
•1600-, 3200-, and 6400-bits-per-second decoding
•Any-phase or single-phase decoding
•Uses standard Serial Peripheral Interface (SPI) in Slave mode
•Allows low current Stop mode operation of host processor
•Highly programmable receiver control
•Real-time clock time base
•FLEX software fragmentation and group messaging support
•Real time clock over-the-air update support
•Compatible with synthesized receivers
•Low Battery Indication (external detector)
•1.8 to 3.3 V low power operation
•32-pin Thin Quad Flat Pack (TQFP) package
ADDITIONAL SUPPORT
FLEX System Software from Motorola is a family of software components for building world-class products incorporating messaging capabilities. FLEXstack™ Software is specifically designed to support the FLEXchip IC. FLEXstack Software runs on a product host processor and takes care of communicating with the FLEXchip IC and fully interpreting the codewords that are passed to the host from the FLEXchip IC.
DOCUMENTATION
This document is the primary document supporting the MC68175 FLEXchip IC. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information).
MOTOROLA |
MC68175/D, Preliminary |
iii |
MC68175
Documentation
iv |
MC68175/D, Preliminary |
MOTOROLA |
Соседние файлы в папке motorola