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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview	MC54/74HC4016A

Quad Analog Switch/

Multiplexer/Demultiplexer

High±Performance Silicon±Gate CMOS

The MC54/74HC4016A utilizes silicon±gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF± channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power±supply range (from VCC to GND).

The HC4016A is identical in pinout to the metal±gate CMOS MC14016 and MC14066. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal±gate CMOS analog switches.

This device is identical in both function and pinout to the HC4066A. The ON/OFF Control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. For analog switches with voltage±level translators, see the HC4316A. For analog switches with lower RON characteristics, use the HC4066A.

•Fast Switching and Propagation Speeds

•High ON/OFF Output Voltage Ratio

•Low Crosstalk Between Switches

•Diode Protection on All Inputs/Outputs

•Wide Power±Supply Voltage Range (VCC ± GND) = 2.0 to 12.0 Volts

•Analog Input Voltage Range (VCC ± GND) = 2.0 to 12.0 Volts

•Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066

•Low Noise

•Chip Complexity: 32 FETs or 8 Equivalent Gates

		LOGIC DIAGRAM
XA	1	2	YA
XA			YA
A ON/OFF CONTROL	13
XB	4	3	YB
XB			YB
B ON/OFF CONTROL	5		ANALOG
			OUTPUTS/INPUTS
XC	8	9	YC
XC			YC
C ON/OFF CONTROL	6
X	11	10 Y
D			D
D ON/OFF CONTROL	12

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD

PIN 14 = VCC

PIN 7 = GND

		J SUFFIX
14	CERAMIC PACKAGE
14	CASE 632±08
1
		N SUFFIX
14	PLASTIC PACKAGE
14	CASE 646±06
	CASE 646±06
1
		D SUFFIX
14	SOIC PACKAGE
1	CASE 751A±03
		DT SUFFIX
14	TSSOP PACKAGE
1	CASE 948G±01
1
ORDERING INFORMATION
MC54HCXXXXAJ		Ceramic
MC74HCXXXXAN		Plastic
MC74HCXXXXAD		SOIC
MC74HCXXXXADT		TSSOP

PIN ASSIGNMENT

XA	1	14	V
			CC
YA	2	13	A ON/OFF
YA	2	13	CONTROL
			CONTROL
YB	3	12	D ON/OFF
XB			CONTROL
XB	4	11	XD
B ON/OFF	5	10	YD
CONTROL	5	10	YD
C ON/OFF	6	9	YC
CONTROL
GND	7	8	XC

FUNCTION TABLE

On/Off Control	State of
Input	Analog Switch

L	Off
H	On

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10/95

Motorola, Inc. 1995

REV 0

MC54/74HC4016A

MAXIMUM RATINGS*

Symbol	Parameter	Value	Unit	This device contains protection
				circuitry to guard against damage
VCC	Positive DC Supply Voltage (Referenced to GND)	± 0.5 to + 14.0	V

				due to high static voltages or electric
VIS	Analog Input Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V	due to high static voltages or electric
VIS	Analog Input Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V	fields. However, precautions must
				be taken to avoid applications of any
Vin	Digital Input Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V	be taken to avoid applications of any
Vin	Digital Input Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V	voltage higher than maximum rated
I	DC Current Into or Out of Any Pin	± 25	mA	voltages to this high±impedance cir-
				cuit. For proper operation, Vin and
PD	Power Dissipation in Still Air, Plastic or Ceramic DIP²	750	mW	cuit. For proper operation, Vin and
PD	Power Dissipation in Still Air, Plastic or Ceramic DIP²	750	mW	Vout should be constrained to the
	SOIC Package²	500		Vout should be constrained to the
	SOIC Package²	500		range GND v (Vin or Vout) v VCC.
	TSSOP Package²	450		range GND v (Vin or Vout) v VCC.
	TSSOP Package²	450		Unused inputs must always be
				Unused inputs must always be
Tstg	Storage Temperature	± 65 to + 150	_C	tied to an appropriate logic voltage
				level (e.g., either GND or VCC).
TL	Lead Temperature, 1 mm from Case for 10 Seconds		_C	level (e.g., either GND or VCC).
TL	Lead Temperature, 1 mm from Case for 10 Seconds	260	_C	Unused outputs must be left open.
	(Plastic DIP, SOIC or TSSOP Package)	260		I/O pins must be connected to a
	(Ceramic DIP)	300		I/O pins must be connected to a
	(Ceramic DIP)	300		properly terminated line or bus.
				properly terminated line or bus.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C

SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter			Min	Max	Unit

VCC	Positive DC Supply Voltage (Referenced to GND)			2.0	12.0	V
VIS	Analog Input Voltage (Referenced to GND)			GND	VCC	V
Vin	Digital Input Voltage (Referenced to GND)			GND	VCC	V
VIO*	Static or Dynamic Voltage Across Switch			Ð	1.2	V
TA	Operating Temperature, All Package Types			± 55	+ 125	_C
tr, tf	Input Rise and Fall Time, ON/OFF	VCC = 2.0 V		0	1000	ns
	Control Inputs (Figure 10)	VCC = 3.0 V		0	600
		VCC = 4.5	V	0	500
		VCC = 9.0	V	0	400
	VCC = 12.0		V	0	250

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit

VIH	Minimum High±Level Voltage	Ron = per spec	2.0	1.5	1.5	1.5	V
	ON/OFF Control Inputs		3.0	2.1	2.1	2.1
			4.5	3.15	3.15	3.15
			9.0	6.3	6.3	6.3
			12.0	8.4	8.4	8.4

VIL	Maximum Low±Level Voltage	Ron = per spec	2.0	0.5	0.5	0.5	V
	ON/OFF Control Inputs		3.0	0.9	0.9	0.9
			4.5	1.35	1.35	1.35
			9.0	2.70	2.70	2.70
			12.0	3.6	3.6	3.6

MOTOROLA

3±2

MC54/74HC4016A

DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND)

				Guaranteed Limit

			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit

Iin	Maximum Input Leakage Current,	Vin = VCC or GND	12.0	±0.1	±1.0	±1.0	μA
	ON/OFF Control Inputs
							μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	2	20	40	μA
	Current (per Package)	VIO = 0 V	12.0	4	40	160

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit

Ron	Maximum ªONº Resistance	Vin = VIH	2.0²	Ð	Ð	Ð	Ω
		VIS = VCC to GND	4.5	160	200	240
		IS v 2.0 mA (Figures 1, 2)	9.0	90	110	130
			12.0	90	110	130

		Vin = VIH	2.0	Ð	Ð	Ð
		VIS = VCC or GND (Endpoints)	4.5	90	115	140
		IS v 2.0 mA (Figures 1, 2)	9.0	70	90	105
			12.0	70	90	105

Ron	Maximum Difference in ªONº	Vin VIH	2.0	Ð	Ð	Ð	Ω
	Resistance Between Any Two	VIS = 1/2 (VCC ± GND)	4.5	20	25	30
	Channels in the Same Package	IS v 2.0 mA	9.0	15	20	25
			12.0	15	20	25

Ioff	Maximum Off±Channel Leakage	Vin = VIL	12.0	0.1	0.5	1.0	μA
	Current, Any One Channel	VIO = VCC or GND
		Switch Off (Figure 3)

Ion	Maximum On±Channel Leakage	Vin = VIH	12.0	0.1	0.5	1.0	μA
	Current, Any One Channel	VIS = VCC or GND
		(Figure 4)

²At supply voltage (V CC ± GND) approaching 3 V the analog switch±on resistance becomes extremely non±linear. Therefore, for low±voltage operation, it is recommended that these devices only be used to control digital signals.

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)

			Guaranteed Limit
		VCC
		VCC	± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit

tPLH,	Maximum Propagation Delay, Analog Input to Analog Output	2.0	40	50	60	ns
tPHL	(Figures 8 and 9)	4.5	5	7	8
		9.0	5	7	8
		12.0	5	7	8

tPLZ,	Maximum Propagation Delay, ON/OFF Control to Analog Output	2.0	80	90	110	ns
tPHZ	(Figures 10 and 11)	4.5	20	25	35
		9.0	20	25	35
		12.0	20	25	35

tPZL,	Maximum Propagation Delay, ON/OFF Control to Analog Output	2.0	80	90	100	ns
tPZH	(Figures 10 and 11)	4.5	20	25	30
		9.0	20	25	30
		12.0	20	25	30

3±3

MOTOROLA

MC54/74HC4016A

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)

Guaranteed Limit

VCC

± 55 to

Symbol

Parameter

25_C

v 85_C

v 125_C

Unit

Maximum Capacitance

ON/OFF Control Input

Control Input = GND

Analog I/O

Feedthrough

1.0

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Switch)* (Figure 13)

* Used to determine the no±load dynamic power consumption: P = C

2f + I

. For load considerations, see Chapter 2 of the

Motorola High±Speed CMOS Data Book (DL129/D).

ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND unless noted)

				Limit*
			VCC	25_C
Symbol	Parameter	Test Conditions	V	54/74HC	Unit

BW	Maximum On±Channel Bandwidth or	fin = 1 MHz Sine Wave	4.5	150	MHz
	Minimum Frequency Response	Adjust fin Voltage to Obtain 0 dBm at VOS	9.0	160
	(Figure 5)	Increase fin Frequency Until dB Meter Reads ± 3 dB	12.0	160
		RL = 50 Ω, CL = 10 pF
Ð	Off±Channel Feedthrough Isolation	fin Sine Wave	4.5	± 50	dB
	(Figure 6)	Adjust fin Voltage to Obtain 0 dBm at VIS	9.0	± 50
		fin = 10 kHz, RL = 600 Ω, CL = 50 pF	12.0	± 50
		fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF	4.5	± 40
			9.0	± 40
			12.0	± 40

Ð	Feedthrough Noise, Control to Switch	Vin v 1 MHz Square Wave (tr = tf = 6 ns)	4.5	60	mVPP
	(Figure 7)	Adjust RL at Setup so that IS = 0 A	9.0	130
		RL = 600 Ω, CL = 50 pF	12.0	200
		RL = 10 kΩ, CL = 10 pF	4.5	30
			9.0	65
			12.0	100

Ð	Crosstalk Between Any Two Switches	fin Sine Wave	4.5	± 70	dB
	(Figure 12)	Adjust fin Voltage to Obtain 0 dBm at VIS	9.0	± 70
		fin = 10 kHz, RL = 600 Ω, CL = 50 pF	12.0	± 70
		fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF	4.5	± 80
			9.0	± 80
			12.0	± 80

THD	Total Harmonic Distortion	fin = 1 kHz, RL = 10 kΩ, CL = 50 pF			%
	(Figure 14)	THD = THDMeasured ± THDSource
		VIS = 4.0 VPP sine wave	4.5	0.10
		VIS = 8.0 VPP sine wave	9.0	0.06
		VIS = 11.0 VPP sine wave	12.0	0.04

* Guaranteed limits not tested. Determined by design and verified by qualification.

MOTOROLA

3±4

	3000
	3000
(OHMS)	2500
	2500
	2000
RESISTANCE	2000									TBD
RESISTANCE

	1500
, ON	1000
on
R	500
	500
	0
	0		.25			.50	.75	1.00			1.25	1.5	1.75 2.00
	0		.25			.50	.75	1.00			1.25	1.5	1.75 2.00
				Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND
			Figure 1a. Typical On Resistance, VCC = 2.0 V
	160
	160
(OHMS)	140
	140
	120
	120
RESISTANCE	100
	100								TBD
	60								TBD
, ON	80
	40

on
on
R	20


	0
	0
	0		.5		1.0	1.5	2.0	2.5		3.0	3.5	4.0	4.5	5.0	5.5	6.0
				Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND
			Figure 1c. Typical On Resistance, VCC = 6.0 V
	80
	80
(OHMS)	70
	70
	60
	60
RESISTANCE	50
	50								TBD
	30								TBD
, ON	40
	20

on
on
R	10


	0
	0	0	1.0		2.0	3.0	4.0	5.0		6.0	7.0	8.0	9.0	10.0	11.0	12.0
				Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1e. Typical On Resistance, VCC = 12.0 V

MC54/74HC4016A

	300
	300
(OHMS)	250
	250
	200
RESISTANCE	200					TBD
RESISTANCE

	150
, ON	100
on
R	50
	50
	0
	0	.5	1.0	1.5	2.0		2.5	3.0	3.5	4.0	4.5
	0	.5	1.0	1.5	2.0		2.5	3.0	3.5	4.0	4.5
		Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND
		Figure 1b. Typical On Resistance, VCC = 4.5 V
	120
	120
(OHMS)	100
	100
	80
RESISTANCE	60					TBD
						TBD

, ON	40
	40

on	20
R	20
	0
	0	1.0	2.0	3.0	4.0		5.0	6.0	7.0	8.0	9.0
	0	1.0	2.0	3.0	4.0		5.0	6.0	7.0	8.0	9.0

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1d. Typical On Resistance, VCC = 9.0 V

PLOTTER

PROGRAMMABLE

POWER MINI COMPUTER DC ANALYZER SUPPLY

±	+	VCC
		VCC
		DEVICE
		UNDER TEST
	ANALOG IN	COMMON OUT
		GND

Figure 2. On Resistance Test Set±Up

3±5

MOTOROLA

MC54/74HC4016A

VCC
				VCC	VCC			VCC
GND			14		VCC		14
	A				A		ON	N/C
VCC	A		OFF		GND
			SELECTED	VIL			SELECTED	VIH
		7	CONTROL			7	CONTROL
		7	INPUT			7	INPUT
			INPUT				INPUT
Figure 3. Maximum Off Channel Leakage Current,					Figure 4. Maximum On Channel Leakage Current,
	Any One Channel, Test Set±Up				Channel to Channel, Test Set±Up

		V	VOS
		CC
		14
fin		ON		dB
	0.1μF		CL*	dB
	0.1μF			METER
				METER
		SELECTED	VCC
	7	CONTROL
	7	INPUT
		INPUT

*Includes all probe and jig capacitance.

Figure 5. Maximum On±Channel Bandwidth

Test Set±Up

	V	V	VOS
	IS	CC
		14
fin		OFF		dB
0.1μF			CL*	dB
0.1μF	RL			METER
	RL			METER

SELECTED

CONTROL

INPUT

*Includes all probe and jig capacitance.

Figure 6. Off±Channel Feedthrough Isolation,

Test Set±Up

V		VCC	V
CC/2			CC/2
		14
RL			RL
		OFF/ON	VOS
		OFF/ON	IS
			CL*
		SELECTED
Vin ≤ 1 MHz	7	CONTROL
Vin ≤ 1 MHz	7	INPUT
tr = tf = 6 ns
VCC	CONTROL
GND	CONTROL
GND

*Includes all probe and jig capacitance.

Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set±Up

VCC

50%

ANALOG IN

GND

tPLH

tPHL

50%

ANALOG OUT

Figure 8. Propagation Delays, Analog In to Analog Out

MOTOROLA

3±6

MC54/74HC4016A

VCC

ANALOG IN

ANALOG OUT TEST

POINT

SELECTED

CL*

VCC

CONTROL

INPUT

*Includes all probe and jig capacitance.

CONTROL	90%		VCC
CONTROL	50%
	50%
	10%		GND
	tPZL	tPLZ	HIGH
			HIGH
	50%		IMPEDANCE
	50%	10%
		10%	VOL
ANALOG			VOL
ANALOG	tPZH	tPHZ
OUT	tPZH	tPHZ	VOH
	50%	90%	VOH
	50%		HIGH
			HIGH
			IMPEDANCE

Figure 9. Propagation Delay Test Set±Up	Figure 10. Propagation Delay, ON/OFF Control
	to Analog Out

	POSITION	1 WHEN TESTING tPHZ AND tPZH
1	POSITION	2 WHEN TESTING tPLZ AND tPZL
2		VCC
VCC		VCC
VCC		14	1 kΩ
1			TEST
		ON/OFF	TEST
2		ON/OFF	POINT
2			POINT
			CL*
	SELECTED
	CONTROL
	INPUT
	7

*Includes all probe and jig capacitance.

Figure 11. Propagation Delay Test Set±Up

VCC

NC		OFF/ON			NC

SELECTED 7 CONTROL INPUT

ON/OFF CONTROL

Figure 13. Power Dissipation Capacitance

Test Set±Up

VIS		VCC
		VCC
RL		14			VOS
RL					VOS
fin	ON
0.1 μF
	OFF
VCC OR GND		RL	CL*	RL	CL*
RL	SELECTED
	SELECTED
	CONTROL	VCC/2		VCC/2
	INPUT	VCC/2		VCC/2
	INPUT
	7
VCC/2
*Includes all probe and jig capacitance

Figure 12. Crosstalk Between Any Two Switches,

Test Set±Up

VIS	VCC		V
			OS
0.1 μF				TO
fin				TO
fin	ON			DISTORTION
		RL	CL*	METER
		VCC/2
	SELECTED	VCC
7	CONTROL
	INPUT

*Includes all probe and jig capacitance.

Figure 14. Total Harmonic Distortion, Test Set±Up

3±7

MOTOROLA

MC54/74HC4016A

	0
	± 10	FUNDAMENTAL FREQUENCY
	± 20
	± 30
dBm	± 40
dBm	± 50	DEVICE
	± 50
	± 60
	± 60	SOURCE
	± 70	SOURCE
	± 70
	± 80
	± 90
	± 100	2.0	3.0
	1.0	2.0	3.0
		FREQUENCY (kHz)

Figure 15. Plot, Harmonic Distortion

APPLICATION INFORMATION

The ON/OFF Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins.

The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example

below, the difference between VCC and GND is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak±to±peak can be controlled.

When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn±on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MO sorbs (Motorola high current surge protectors). MO sorbs are fast turn±on devices ideally suited for precise DC protection with no inherent wear±out mechanism.

VCC = 12 V

+ 12 V

ANALOG I/O

ANALOG O/I

0 V

+ 12 V

SELECTED

CONTROL

OTHER CONTROL

INPUT

INPUTS

(VCC OR GND)

Figure 16. 12 V Application

VCC		VCC
Dx	14	Dx
	ON

VCC

SELECTED

CONTROL

OTHER CONTROL

INPUT

INPUTS

(VCC OR GND)

Figure 17. Transient Suppressor Application

MOTOROLA

3±8

									MC54/74HC4016A
+ 5 V							+ 5 V
	ANALOG		14		ANALOG			ANALOG	14	ANALOG
	ANALOG				ANALOG			ANALOG		ANALOG
	SIGNALS				SIGNALS			SIGNALS		SIGNALS
R*	R* R* R*	HC4016						HCT	HC4016
LSTTL/							LSTTL/	BUFFER
NMOS	5						NMOS	5
	6	CONTROL						6	CONTROL
		CONTROL							CONTROL
	14	INPUTS						14	INPUTS
	15		7					15	7
			7						7
	R* = 2 TO 10 kΩ
a. Using Pull-Up Resistors								b. Using HCT Buffer
			Figure 18. LSTTL/NMOS to HCMOS Interface
			VDD = 5 V				VCC = 5 TO 12 V
		13	1	16	ANALOG		14	ANALOG
		3			SIGNALS			SIGNALS
		5					HC4016
		7	MC14504		2	5
		9			4	6	CONTROL
		11			6	14	INPUTS
		14	8		10	15	7
			8				7

Figure 19. TTL/NMOS±to±CMOS Level Converter Analog Signal Peak±to±Peak Greater than 5 V (Also see HC4316A)

CHANNEL 4

1 OF 4

SWITCHES

CHANNEL 3

1 OF 4

SWITCHES

COMMON I/O

CHANNEL 2

1 OF 4

SWITCHES

CHANNEL 1

1 OF 4

OUTPUT

SWITCHES

INPUT

SWITCHES

EQUIVALENT

0.01 μF

CONTROL INPUTS

3±9

MOTOROLA

MC54/74HC4016A

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC DIP PACKAGE

CASE 632±08

ISSUE Y

	-A-
14	8
	-B-
1	7

		C
-T-		K
SEATING		K
PLANE
F	G	N

D 14 PL

0.25 (0.010) M T A S

					NOTES:
					1. DIMENSIONING AND TOLERANCING PER ANSI
					Y14.5M, 1982.
					2. CONTROLLING DIMENSION: INCH.
					3. DIMENSION L TO CENTER OF LEAD WHEN
					FORMED PARALLEL.
					4. DIMESNION F MAY NARROW TO 0.76 (0.030)
L					WHERE THE LEAD ENTERS THE CERAMIC
L					BODY.
						INCHES		MILLIMETERS
					DIM	MIN	MAX	MIN	MAX
					A	0.750	0.785	19.05	19.94
					B	0.245	0.280	6.23	7.11
					C	0.155	0.200	3.94	5.08
					D	0.015	0.020	0.39	0.50
					F	0.055	0.065	1.40	1.65
M					G	0.100 BSC		2.54 BSC
M					J	0.008	0.015	0.21	0.38
J 14 PL					K	0.125	0.170	3.18	4.31
J 14 PL					L	0.300 BSC		7.62 BSC
0.25 (0.010)	M	T	B	S	M	0°	15°	0°	15°
					N	0.020	0.040	0.51	1.01

N SUFFIX

PLASTIC DIP PACKAGE

CASE 646±06

ISSUE L

14		8
			B
1		7
	A
	F			L
				C
			N	J
			N
			SEATING	K
H	G	D	PLANE	K
			PLANE	M
				M

NOTES:

1.LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.

2.DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

3.DIMENSION B DOES NOT INCLUDE MOLD FLASH.

4.ROUNDED CORNERS OPTIONAL.

	INCHES		MILLIMETERS
DIM	MIN	MAX	MIN	MAX
A	0.715	0.770	18.16	19.56
B	0.240	0.260	6.10	6.60
C	0.145	0.185	3.69	4.69
D	0.015	0.021	0.38	0.53
F	0.040	0.070	1.02	1.78
G	0.100 BSC		2.54 BSC
H	0.052	0.095	1.32	2.41
J	0.008	0.015	0.20	0.38
K	0.115	0.135	2.92	3.43
L	0.300 BSC		7.62 BSC
M	0	10	0	10
N	0.015	0.039	0.39	1.01

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