Адаптивная дифференциальная импульсно-кодовая модуляция / 2014ADPCM

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Hardware Implementation of Adaptive-Differential Pulse Code Modulation

Speech Compression Algorithm

Article · January 2015

DOI: 10.21742/ijsda.2014.2.2.01

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International Journal of Smart Device and Appliance

Vol.2, No.2 (2014)

Hardware Implementation of Adaptive-Differential Pulse Code

Modulation Speech Compression Algorithm

Marcus L. George, Geetam Singh Tomar

Dept of Electrical and Computer Engineering

University of West Indies, St. Augustine, Trinidad and Tobago marcus.george99@yahoo.com, gstomar@ieee.org

Abstract

Voice-over Internet Protocol (VoIP) telephony is increasingly becoming a variant telecommunication technology that one day may surpass the old analog and digital telephone systems. The Quality-of-Service (QoS) factor is an important parameter to be considered when measuring the performance of a VoIP system. Many factors may influence the QoS of a given VoIP system. Some of these factors are delay, jitter and packet loss. This paper served to demonstrate that the algorithmic delay (latency) of the Adaptive-Differential Pulse Code Modulation (ADPCM) speech compression algorithm which has originally been implemented in software can be significantly reduced by implementation in hardware. The ADPCM speech compression algorithm is first implemented, verified to demonstrate equivalence and then validated by comparing the latency of the hardware-implemented speech compression algorithm with that of existing an software implementation.

Keywords: Adaptive-Differential Pulse Code Modulation; Hardware implementation; Speech compression algorithm.

1. Introduction

A speech signal is a sound formed by humans in order to communicate. Like all other sound, it is a perturbation of the atmospheric pressure that travels in the form of a sound wave [7]. To transport speech over communication networks, the speech signal must be transformed from a sound wave to an electrical signal. This is usually done with a microphone and the result is an electrical signal where the voltage varies with the pressure of the speech signal. VoIP is the transmission of real-time voice traffic over an internet protocol (IP) data network [3]. VoIP is an alternative to the Public Switched Telephone Network (PSTN) [9] when placing a telephone call between two or more parties. Since both sides of a telephone conversation can speak and listen, each side must be able to code and decode voice data. Coding and decoding of speech is done using speech compression algorithms. Waveform-based speech compression algorithms are the simplest form of speech compression algorithms. They represent individual samples from the analog speech waveform in a digital form. Speech compression algorithms can be implemented in three ways: 1) software; 2) hardware-software co-design; and 3) hardware. The software implementations of speech compression algorithms such as in [8] have provided users with high speech quality and low terminal price. However the software implementations of these speech compression algorithms require a significant amount of time for their execution. The implementations of speech compression algorithms that take advantage of the hardware-software co-design model such as in [8] have also provided users with high speech quality and low terminal price. Although these implementations of speech compression algorithms required less time for

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their execution than the speech compression algorithms implemented entirely in software, they still require too much time for their execution. It can be assumed from the information previously presented that the implementation of the speech compression algorithms which utilize the hardware-software co-design model may have been speeded up because of the fact that some components have been implemented in hardware. This also indicates to us that that algorithmic delay of speech compression algorithms that were implemented entirely in software can be accelerated by implementation in hardware. To further solve the problem of large delays required for the execution of speech compression algorithms, this paper will present the implementation of the ADPCM speech compression algorithm entirely in hardware and demonstrate that the hardware implementation significantly reduces the algorithmic delay of the ADPCM speech compression algorithm originally implemented in software.

2. OVERVIEW OF ADPCM SPEECH COMPRESSION ALGORITHM

ADPCM (ITU-T G.726) is a waveform-based compression algorithm. It works by coding the difference between two consecutive samples of PCM. ADPCM retains advantages of PCM, with a reduced bit rate. ITU-T G.726 [5] uses adaptive quantization. Adaptive quantization is the quantization process where the step size is varied based on the changes of the input signal as a means of achieving efficient compression. Sample differences may be represented with 5, 4, 3 or 2 bits corresponding to bit rates 40kbit/s, 32kbit/s, 24kbit/s and 16kbit/s respectively.

[5] specifies that an 8-bit μ-law/A-law PCM word should be reduced to a 4-bit word for 32kbit/s ADPCM operation, resulting in the reduction of the bit rate by a factor of two. The principle of ADPCM involves using knowledge of the signal in the past time to predict it in the future. The resulting signal is the error of the prediction.

3. PROFILING OF SOFTWARE IMPLEMNTATIONS OF ADPCM

The latency of the software implementation of ADPCM from Sun Microsystems was obtained using the procedure outlined in [2]. Because of the GPROF time resolution each encoder/decoder was run over 1,000,000 inputs. To discount the effects of other programs/overhead the process was repeated three times for each encoder/decoder considered. The total was divided by 3,000,000 to give an estimate of the latency. Table I gives the results of the software profiling for the latency (in cycles) of the software implementation of ADPCM encoders and decoders. [2] demonstrates how latency in nanoseconds was converted to cycles.

TABLE 1. Latency of software implemented ADPCM speech compression algorithm from Sun Microsystems for bit rate of 32kbit/s

4. DESIGN OF THE ADPCM SPEECH COMPRESSION ALGORITHM

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The ADPCM encoder was designed by applying the hardware design technique outlined in [2]. Data in 8-bit μ-law/A-law PCM format is converted to 16-bit uniform PCM format, sL(k) by the input PCM conversion unit. The difference computation unit then computes the difference between the 16-bit uniform PCM data the estimate of the previous sample se(k) to give the difference signal d(k). The difference signal and previous scale factor y(k-1) are utilized in the computation of the 4-bit ADPCM word I(k) by the adaptive quantizer. The ADPCM word is input to the inverse adaptive quantizer, adaptation speed control and quantizer scale factor units for the prediction of the previous speech sample.

The inverse adaptive quantizer estimates the difference signal dl(k) using the ADPCM word and the previous scale factor. The adaptation speed control block computes the controlling parameter al (k) at the selected data rate using the ADPCM signal, the previous scale factor and the previous tone and transition parameters td(k-1) and tr(k-1) respectively. The quantizer scale factor adaptation unit computes the scale factor y(k) using the controlling parameter al(k) and ADPCM signal. The slow-locked scale factor yl(k) and the previous predictor coefficient a2(k-1) are used by the tone and transition computer in the computation of the tone and transition parameters td(k) and tr(k) respectively.

The adaptive predictor then computes the signal estimate se (k) and predictor coefficients using the transition parameter, estimate of the difference signal dl(k) and the previous reconstructed signal sr(k-1). Finally the reconstructed signal calculator computes the reconstructed signal sr(k) using the signal estimate se(k) and the estimate of the difference signal.

Shift registers were used in order to store the present value of the difference signal along with the previous six difference signal values for use by the adaptive predictor. This approach was also used to store the present and previous scale factor values for use by several encoder units.

A. Input PCM Format Conversion

This unit converts data in 8-bit μ-law/A-law PCM format to 16-bit uniform PCM. This unit consists of two units. The first unit is the PCM decoder[4]. The second unit converts data in 14-bit uniform PCM format to 16-bit uniform PCM format using [5].

B. Difference Computation

This difference computation unit computes the difference signal d(k) by finding the difference between the 16-bit uniform PCM signal SL(k), and the signal estimate Se(k) from the adaptive predictor. The difference computation unit was represented as a 16-bit binary subtractor. A LUT could have been used instead, however a 16-bit binary subtractor was chosen since less hardware was required.

C. Adaptive Quantizer

This adaptive quantizer unit computes the ADPCM word I(k) [5] by quantizing the difference signal d(k) for operation at 32kbit/s using 8-level non-uniform adaptive quantizer. A LUT was used to output the ADPCM codeword for the specified data rate and the difference between the scale factor and the log of the difference signal.

D. Inverse Adaptive Quantizer

This inverse adaptive quantizer unit computes a quantized version of the difference signal, dq(k) using the ADPCM codeword. This unit performs the reverse of the process performed

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by the adaptive quantizer. The quantized version dq(k) of the difference signal is computed by raising 2 to the a power equal to the output of the addition process. An alternative to this was the use of a LUT, however the selected approach was preferred since it required less hardware than the use of a LUT.

E. Quantizer Scale Factor Adaptation

The quantizer scale factor adaptation unit computes the scale factor y(k) [5] using the ADPCM word I(k), and the controlling parameter al(k) from the adaptive speed control unit. A LUT was used to determine the discrete function W[I(k)] (CCITT 1990) for the specified ADPCM word I(k).

A structural unit Model A was used in the design of several units of the ADPCM encoder. Model A unit computes Equation 1 and was designed using the hardware design technique presented in [2]. An arithmetic logic unit (ALU) was used to allow both addition and subtraction depending on the sign of variable q(x).

Modules A and B compute the fast (locked) scale factor, yu(k) [5] and slow (locked) scale factor, yl(k) [5] respectively using the copies of Model A because their algorithms were similar to that of Equation 1. Module C computed the scale factor y(k) [5] using copy of Model A because the algorithm for module C was also similar to that of Equation 1. The only differences between Modules A, B and C are the value of the inputs and constants used.

F. Adaptation Speed Control

The adaptation speed control unit computes the controlling parameter al(k). A LUT was used to determine the discrete function F[I(k)] [5] for the specified ADPCM word I(k). Module A and B compute the relatively short term average dms(k) and relatively long term average dml(k) respectfully of the discrete function F[I(k)] [5] using copies of unit Model A because their algorithms were similar to that of Equation 1.

Module C computes the variable ap(k) [5] using the previous value of the variable ap(k-1), the relatively short-term and long-term averages, the scale factor from the quantization scale factor unit, and the tone and transition parameters td(k) and tr(k) respectively. A subtractor along with two multipliers were used in order to compute the possible values of the controlling parameter ap(k) while an encoder was used to assign the possible values of controlling parameter based on the status of the scale factor and the tone and transition parameters td(k) and tr(k). A multiplexer unit could have been used instead of an encoder. However comparators would have been required to determine if the values of the scale factor and the tone and transition parameters satisfy the ranges required for the selection of the possible values of the controlling parameters. Module D computed the controlling parameter [5]. This was represented by an encoder which compared the variable ap(k) with 1 and outputs either variable ap(k) or 1 based on which is greater.

G. Adaptive Predictor

The adaptive predictor computed the signal estimate se(k) from the quantized difference signal dq(k). Two adaptive predictor structures were used - a sixth order section that models zeros and a second order section that models poles in the input signal [5]. The adaptive predictor consists of three units in addition to several multiplexers and shift-registers.

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Module A (predictor coefficient computation (PCC) unit) accepts inputs the transition parameter, difference signal and predictor values p(k) and computes the predictor coefficients a1(k), a2(k) and bi(k) [5]. Module A consists of four modules. A structural unit Model B was used in the design of several of these units. Model B unit implements Equation 2. The only difference between Equation 2 and Equation 1 is that variable q(x) of Equation 1 is replaced by sgn[q(k)q(k-1)] in Equation 2. Therefore Model B was designed using a copy of Model A and a sign decoder unit. The sign decoder determined the sign of the output resulting from the product of the two signed values q(k) and q(k-1) which was connected to the opcode port of Model A for selection of the arithmetic process to be carried out.

g(x) (1 2 n ) p(x) (2 m ) sgn[q(k)] sgn[q(k 1)] (2)

Module AB of the PCC unit accepts the previous predictor coefficient a1(k-1), and the current and previous predictor values p(k) and p(k-1) and computes the new predictor coefficient a1(k). Module B consists of a copy of Model B and a shift register. The shift register was used to store the current and previous values of the predictor coefficient a1(k) and a1(k-1) respectively which are required for the computation of the signal estimate.

Module AC of the PCC unit accepts the inputs a2(k-1), f[a1(k)], p(k) and p(k-2) and computes the predictor coefficient a2(k). This unit consists of a copy of Model A, along with a sign manipulator, two sign decoders. The sign decoders were used to determine the sign of the output resulting from the product of the two signed values inputted. The sign manipulator accepts an input value (f[a1(k)] in this case) along with the sign bit of two numbers and replaces the sign of the inputted value with the sign of the product resulting from the multiplication of the two numbers in which these sign bits were extracted from. The result is used in the computation of the predictor coefficient a2(k) using Model A. The shift register was used to store the current as well as previous values of the predictor coefficient a2(k) and a2(k-1) respectively which are required for the computation of the signal estimate.

Module AD accepts the previous predictor coefficients bi(k-1) (i=1,..,6) and the present and previous difference signals dp(k) and dp(k-i) and computes the present predictor coefficients bi(k). The previous predictor coefficients bi(k-1) were stored using a shift register. When the operation of Module AD is initiated the previous coefficients bi(k-1) are stored in the 150 bit hold register. The 6-line to 1-line multiplexer along with a modulo 6 counter are used to select one of the 6 predictor coefficients for i=1,..,6 to be used by the a copy of Model B for the computation of the new predictor coefficients bi(k) which are then stored in the shift register for use in future adaptive predictions.

Module B and C along with a binary adder are used in the computation of the signal estimate [5]. Module B computes of the adaptive predictor computes the second order section of the signal estimate algorithm [5] that models poles while Module C computes the sixth order section that models zeros. Shift registers were used in order to store the current and previous two values of the signal estimate and predictor values. The multiplexers are used to allow the selection of the signal estimates, previous predictor coefficients and previous difference signal values required by module B and C for the computation of the signal estimate.

H. Reconstructed Signal Calculator

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This reconstructed signal calculator unit computed the sum of the previous signal estimate se(k-1), and the quantized difference signal dq(k-i). The reconstructed signal calculator was represented by a 16-bit binary adder.

I.Tone and Transition Detector

The tone and transition detector generated the tone parameter, td(k) and transition parameter, tr(k). The tone and transition parameters can take values 0 or 1. The tone and transition detector consisted of a base 24.2 unit which was used to raise 24.2 to the power of the previous scale factor, in addition to an encoder which determines the tone and transition parameters based on the values of predictor coefficient a2(k-1), the unsigned difference signal and the result of the base 24.2 unit.

J. ADPCM Decoder Design

The ADPCM decoder was designed by applying the hardware design technique outlined in [2]. The ADPCM decoder consisted of several units found in the ADPCM encoder outlined in the same way. The reconstructed signal sr(k) developed by the reconstructed signal calculator in 16-bit uniform PCM format was converted back to 8-bit μ/A-law PCM format by the output PCM conversion unit. The synchronous coding adjustment block then processes the output signal sd(k). A main controller unit was used in the control of the entire ADPCM encoder.

K. Output PCM Format Conversion

This unit converts data in 16-bit uniform PCM format to 8-bit μ-law/A-law PCM. This unit consists of two units. The first unit converts data in 16-bit uniform PCM format to 14-bit uniform PCM using [5].

L. Synchronous Coding Adjustment

The synchronous coding adjustment unit prevents cumulative distortion occurring on synchronous tandem codings (ADPCM - PCM - ADPCM, etc) [5]. The synchronous coding adjustment unit was represented by an encoder unit. The quantized version of the difference signal obtained from the inverse adaptive quantizer was required for the synchronous coding adjustment process. The upper and lower boundaries of the difference signal were determined by rounding up and rounding down the difference signal respectively. The difference between the signal estimate and the 16-bit uniform PCM sample is then computed and used along with the upper and lower boundaries of the quantized version of the difference signal to determine the adjusted μ-law/A-law PCM output.

5. HARDWARE IMPLEMENTATION OF THE ADPCM SPEECH COMPRESSION ALGORITHM

The hardware implementation of the ADPCM speech compression algorithm was done in VHDL using the Xilinx 11.1 ISE environment. The reasons for selecting VHDL were presented in [2]. Fixed point units obtained from [1] and the Xilinx IPcore generator were utilized in the hardware implementation of the designed ADPCM speech compression algorithms. Floating point units could have been used instead of fixed point units because they provide enhanced performance over fixed point and integer units due to their large dynamic range. However fixed point unit were used instead because they require less

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hardware than floating point units, have shorter latencies and introduce less errors to the arithmetic than floating point units.

All units of the ADPCM encoder and decoder were port-mapped together using knowledge gained in [10]. All system modules and sub-modules consisting of more than one component were sequenced using FSM control units that were designed and implemented as demonstrated in [2]. After implementing the ADPCM speech compression algorithm in hardware, it was synthesized in the Xilinx 11.1 ISE environment in preparation for verification and validation.

6. VERIFICATION AND VALIDATION OF THE ADPCM SPEECH COMPRESSION ALGORITHM

Test vectors for ADPCM, consisting of the input test cases and the expected outputs were obtained from the [6]. Test cases were selected with input samples belonging to each of the following categories: small, intermediate and large values, positive and negative values. The actual outputs of the hardware-implemented ADPCM encoder were obtained through simulation using Modelsim XE 6.4b. The actual outputs were compared to the expected outputs from the ITU-T test vectors to verify that the hardware-implemented ADPCM encoder correctly compressed the input test sequences.

The expected outputs of the ADPCM encoder obtained from [6] were used as the inputs to the hardware-implemented ADPCM decoder. The expected outputs for the ADPCM decoder were obtained from [6]. The actual outputs of the hardware-implemented ADPCM decoder were obtained through simulation using Modelsim XE 6.4b. The actual outputs of the hardware-implemented ADPCM decoder were compared to the expected outputs of the ADPCM decoder obtained from [6] to verify that the hardware-implemented ADPCM decoder correctly decompressed the selected input test sequences.

The verification test results (Table II and Table III) indicate that actual outputs of the ADPCM encoder and decoder corresponded to the expected results from [6].

TABLE2. Verification tests results for the ADPCM (32kbit/s Operation) Encoder and Decoder in u-law mode

TABLE 3. Verification tests results for the ADPCM (32kbit/s Operation) Encoder and Decoder in A-law mode

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The latency of both hardware-implemented ADPCM encoder and decoder were obtained by applying the technique outlined in [2]. The results of the validation tests (Table IV) indicate that the latency of hardware ADPCM encoder was 3621 times shorter than the latency of software ADPCM encoder, while the latency of the hardware ADPCM decoder was 2527 times shorter than the latency of the software ADPCM decoder.

TABLE 4. Performance Comparison of Hardware and Software

Implementations of ADPCM

7. DISCUSSION

From the verification results it can be deduced that the actual outputs of the ADPCM encoder and decoder corresponded to the expected outputs from [6] and hence correctly compressed and decompressed the input samples respectively and hence can be considered equivalent implementations of ADPCM.

The validation results demonstrated that the latency (algorithmic delay) of both the hardware-implemented ADPCM encoder and decoder were 3621 and 2527 times shorter than the latency of their software counter-parts from Sun Microsystem respectively. This indicated that the algorithmic delay of the ADPCM speech compression algorithm which has originally been implemented in software was significantly reduced by implementation in hardware.

The main advantage of using hardware is speed as these algorithms use a great deal of processing power for computation. Software has the disadvantage of being slower but however has the benefit of flexibility. However with the advent of reconfigurable computation, FPGAs are capable of providing this advantage to embedded systems designers. The speech compression algorithms could also have been implemented in hardware using analog circuits instead of digital circuits. However the area used for the implementation of the systems would have been larger and because of the great complexity of the several of the speech compression algorithms the implementation process would have taken more time than if the system was implemented with digital circuits using an HDL. In addition the implementation of the speech compression algorithm in hardware using an HDL was accelerated by the availability of floating-point libraries. Required floating-point units were

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selected from these libraries for use in the implementation of these speech compression algorithms.

8. Conclusions

This paper presented the implementation, verification and validation of the ADPCM speech compression algorithm [5]. A future development for this system is the creation of a prototype to work with the existing VoIP software which can replace the existing softwareimplementation of PCM. This will require the development of an ASIC for each of these speech compression algorithms. ASICs have several advantages over FPGAs. ASICs are relatively faster and more power efficient than FPGAs [11]. FPGA power and delay overheads are due to their programmable switch elements [11]. ASICs however have a reduced production volume compared to FPGAs [11].

References

[1]Bishop, David. 2008. Parametized Floating Point Package. February 27. http://www.vhdl.org/fphdl/vhdl.html (accessed July 17 2009)

[2]George, Marcus. 2010. Hardware Design Procedure: Principles and Practices. DELTA 2011: 6th International Symposium on Electronic Design, Test and Applications. Queenstown, New Zealand.

[3]Halsall, Fred. 1998. Data Communications, Computer Networks and Open Systems. 4th. ed. Wales: Addison-Wesley Publishing Company.

[4]International Telecommunication Union (ITU). 1972. Pulse Code Modulation (PCM) of Voice Frequencies. G.711.

[5]International Telegraph and Telephone Consultative Committee (CCITT). 1990. 40, 32, 24, 16 kbit/s Adaptive-Differential Pulse Code Modulation (ADPCM). G726.

[6]International Telecommunication Union (ITU). 1997. Description of the digital test sequences for the verification of the G.726 40, 32, 24 and 16 kbit/s ADPCM algorithm. G.726 Appendix II Test Vectors (03/91).

[7]Juan, G. R. 1995. Introduction to the Physics and Psycholophysics of Music. 3rd ed. New York: Springer Verlag.

[8]GS Tomar, M.L George, “Open-Lop Pitch Analysis for the Conjugate-Structure Algebraic-Code-Excited Linear -Prediction Speech Compression Algorithm”, Asia-pacific Journal of Multimedia Services Convergence with Art, Humanities and Sociology, Vol.1, No.1, pp. 43-52, 2011

[9]Mishra, Shrindhar, Balaram, Arjun. 2000. Efficient hardware-software co-design for the G.723.1 algorithm targeted at VoIP applications.

[10]Montminy, Christian. 2000. A Study of Speech Compression Algorithms for Voice Over IP. Msc Thesis. Ottawa-Carleton Institute for Electrical and Computer Engineering, University of Ottawa, Canada.

[11]Perry, Douglas. 1998. VHDL. 3rd ed. New York: McGraw-Hill.

[12]Tessier, Russell. 1999. Fast Place and Route Approaches for FPGAs. PhD Thesis. Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, United States of America

[13]GS Tomar, M.L George, “Open-Lop Pitch Analysis for the Conjugate-Structure Algebraic-Code-Excited Linear -Prediction Speech Compression Algorithm”, Asia-pacific Journal of Multimedia Services Convergence with Art, Humanities and Sociology, Vol.1, No.1, pp. 43-52, 2011. DOI: 10.14257/AJMSCAHS.201.06.03

[14]GS Tomar, M.L George, “Open-Lop Pitch Analysis for the Conjugate-Structure Algebraic-Code-Excited Linear -Prediction Speech Compression Algorithm”, Asia-pacific Journal of Multimedia Services

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