5406 Multi-Lane Distribution and Merging

541DSI is a Lane-scalable specification. Applications requiring more bandwidth than that provided by one

542Data Lane may expand the data path to two, three, or four Lanes wide and obtain approximately linear

543increases in peak bus bandwidth. This specification explicitly documents the mapping between application

544data and the serial bit stream to ensure compatibility between host processors and peripherals that make use

545of multiple Lanes.

546Multi-Lane implementations shall use a single common clock signal, shared by all Data Lanes.

547Conceptually, between the PHY and higher functional blocks is a layer that enables multi-Lane operation.

548In the transmitter, shown in Figure 4, this layer distributes a sequence of packet bytes across N Lanes,

549where each Lane is an independent block of logic and interface circuitry. In the receiver, shown in Figure 5,

550the layer collects incoming bytes from N Lanes and consolidates the bytes into complete packets to pass

551into the following packet decomposer.

Copyright © 2005-2006 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member Confidential.

23